Lerong Cheng

Routability checking for three-dimensional architectures

We present a novel symbolic routability checking approach for three-dimensional interconnect layout. The model considered is a general architecture that can fit into different applications, such as ASIC, multichip modules, field-programmable gate arrays, and reconfigurable computing architectures. The method can incrementally incorporate additional constraints driven by timing, performance, and design. We used the latest satisfiability solver to validate the effectiveness of our approach. The experimental results demonstrate the encouraging performance on difficult routing benchmarks.

Congestion estimation for 3-D circuit architectures

Three-dimensional (3-D) routing is an important step in deep submicrometer very large-scale integrated design. Given a 3-D grid graph and a set of two-terminal nets to be routed, we propose a probabilistic model to calculate the routing density (congestion) on each edge of the grid graph. The routing density provides a direct congestion estimation. Our experimental results demonstrate the effectiveness of the method on routing benchmarks.

Congestion estimation for 3D routing

Three-dimensional (3D) routing is an important step in deep sub-micron VLSI design. Given a 3D grid graph and a set of two-terminal nets to be routed, we propose a probabilistic model to calculate the routing density (congestion) on each edge of the grid graph. The routing density provides direct congestion estimation. Our experimental results demonstrate the effectiveness of the method on routing benchmarks.

A fast congestion estimator for routing with bounded detours

Congestion estimation is an important issue for design automation of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and wire planning. A probabilistic model of interconnections enables designers to quickly predict routing congestion. We propose a powerful and fast estimation approach that allows wires to have bounded-length detours to bypass congestions. The method is more realistic and precise than the previous work. The experimental results demonstrate the effectiveness of the method on routing benchmarks.

A hierarchical method for wiring congestion prediction

Interconnect congestion estimation plays an important role in the physical design of integrated circuits. This paper presents a novel probabilistic approach to predicting wiring space in two-dimensional arrays. We propose a hierarchical estimation method to derive approximated upper bounds for wiring space. We use the net density distribution for predicting the routing congestion. Experimental results demonstrate the promising performance of the new approach.

Congestion estimation for hexagonal routing

Interconnect planning is an important issue in VLSI designs. Routing congestion is an important problem during placement. This paper presents a novel approach to estimating the routing congestion on the hexagonal model with bounded-length detours. It is the first probabilistic estimation work on hexagonal topologies. A combinatorial estimation algorithm is presented. The experimental results demonstrate the effectiveness of the method.

A combinatorial congestion estimation approach with generalized detours

Congestion estimation plays an important role in the physical layout of VLSI design. This paper presents a new probabilistic estimation model that improves the previous estimators by relaxing the constraint on detours in a route. The model is more general and realistic for it gives the flexibility for the wires to have wider usage area to bypass the congestion regions and blockages. Given a routing grid and a set of nets to be routed, the model predicts the routing density on each edge of the grid. The routing density provides direct congestion estimation. We compare our estimation results to the actual routing results. Experimental results show the effectiveness of our estimator.

Probabilistic Estimation for Routing Space

Interconnect congestion estimation plays an important role in design automation of VLSI designs. This paper presents a novel probabilistic approach to predict the wiring space in two-dimensional arrays. We propose a hierarchical estimation method to derive approximated upper bounds for the wiring space, and we use the net density distribution to predict the routing congestion. Experimental results demonstrate the promising performance of the approach.

AN ANALYTICAL CONGESTION MODEL WITH BOUNDED-BEND DETOURS

With the increase of the complexity of circuits, fast estimation can provide some vital information for optimal layout decisions. Fast congestion prediction plays an important role in the physical layout of VLSI design. In this paper, we present a probabilistic estimation approach with via minimization constraints. Our model is more realistic than previous models. It has more flexibility for wires to have more usage area to bypass congested regions and blockages. The experiment on routing benchmarks demonstrates the effectiveness of our approach.

Wire congestion estimation in a bounded-bend model

Interconnect congestion estimation plays an important role in the physical design of integrated circuits. Fast congestion analysis prior to global routing enhances the placement quality and improves the routability for the subsequent routing phases. This article presents a novel congestion estimation method for a wire layout with bounded detours and bends. Experimental results on benchmarks demonstrate the efficiency and accuracy of our approach.