William N. N. Hung

Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis

This paper proposes an approach to optimally synthesize quantum circuits by symbolic reachability analysis, where the primary inputs and outputs are basis binary and the internal signals can be nonbinary in a multiple-valued domain. The authors present an optimal synthesis method to minimize quantum cost and some speedup methods with nonoptimal quantum cost. The methods here are applicable to small reversible functions. Unlike previous works that use permutative reversible gates, a lower level library that includes nonpermutative quantum gates is used here. The proposed approach obtains the minimum cost quantum circuits for Miller gate, half adder, and full adder, which are better than previous results. This cost is minimum for any circuit using the set of quantum gates in this paper, where the control qubit of 2-qubit gates is always basis binary. In addition, the minimum quantum cost in the same manner for Fredkin, Peres, and Toffoli gates is proven. The method can also find the best conversion from an irreversible function to a reversible circuit as a byproduct of the generality of its formulation, thus synthesizing in principle arbitrary multi-output Boolean functions with quantum gate library. This paper constitutes the first successful experience of applying formal methods and satisfiability to quantum logic synthesis

Quantum logic synthesis by symbolic reachability analysis

Reversible quantum logic plays an important role in quantum computing. In this paper, we propose an approach to optimally synthesize quantum circuits by symbolic reachability analysis where the primary inputs are purely binary. we use symbolic reachability analysis, a technique most commonly used in model checking (a way of formal verification), to synthesize the optimum quantum circuits. We present an exact synthesis method with optimal quantum cost and a speedup method with non-optimal quantum cost. Both our methods guarantee the synthesizeability of all reversible circuits. Unlike previous works which use permutative reversible gates, we use a lower level library which includes non-permutative quantum gates. For the first time, problems in quantum logic synthesis have been reduced to those of multiple-valued logic synthesis thus reducing the search space and algorithm complexity. We synthesized quantum circuits for gate, half-adder, full-adder, etc. with the smallest cost.. Our approach obtains the minimum cost quantum circuits for Millers gate, half-adder, and full-adder, which are better than previous results. In addition, we prove the minimum quantum cost (using our elementary quantum gates) for Fredkin, Peres, and Toffoli gates. Our work constitutes the first successful experience of applying satisfiability with formal methods to quantum logic synthesis.

Fast synthesis of exact minimal reversible circuits using group theory

We present fast algorithms to synthesize exact minimal reversible circuits for various types of gates and costs. By reducing reversible logic synthesis problems to group theory problems, we use the powerful algebraic software GAP to solve such problems. Our algorithms are not only able to minimize for arbitrary cost functions of gates, but also orders of magnitude faster than the existing approaches to reversible logic synthesis. In addition, we show that the Peres gate is a better choice than the standard Toffoli gate in libraries of universal reversible gates.

Defect-Tolerant CMOL Cell Assignment via Satisfiability

We present a novel CAD approach to cell assignment of CMOL, a hybrid CMOS/molecular circuit architecture. Our method transforms any logically synthesized circuit based on AND/OR/NOT gates to a NOR gate circuit and maps the NOR gates to CMOL. We encode the CMOL cell assignment problem as Boolean conditions. The Boolean constraints are satisfiable if and only if there exists a solution to map all the NOR gates to the CMOL cells. We further investigate various types of static defects for the CMOL architecture and propose a reconfiguration technique that can deal with these defects. We introduce a new CMOL static defect model and provide an automated solution for CMOL cell assignment. Experiments show that our approach can result in smaller area (CMOL cell usage) and better timing delay than prior approach.

BDD minimization by scatter search

Reduced-ordered binary decision diagrams (BDDs) are a data structure for representation and manipulation of Boolean functions. The variable ordering largely influences the size of the BDD, varying from linear to exponential. In this paper, the authors study the BDD minimization problem based on scatter search optimization. Scatter search offers a reasonable compromise between quality (BDD reduction) and time. On smaller benchmarks it delivers almost optimal BDD size with less time than the exact algorithm. For larger benchmarks it delivers smaller BDD sizes than genetic algorithm or simulated annealing at the expense of longer runtime.

A novel fault diagnosis mechanism for wireless sensor networks

This paper considers a novel fault diagnosis mechanism for wireless sensor networks (WSNs). Without additional agents, the built-in and self-organized diagnosis mechanism can monitor each node in real time and identify faulty nodes. As the diagnosis is operated within a cluster of nodes, it can reduce power consumption and communication traffic. We present a modeling of the diagnosis algorithm for WSNs, with a probabilistic analysis of the local and global performances of our approach. Extensive experiments demonstrate the effectiveness of the proposed method.

Bayesian-Network-Based Reliability Analysis of PLC Systems

Reliability analysis is an important part of safety critical programmable logic controller (PLC) systems. The complexity of PLC system reliability analysis arises in handling the complex relations among the hardware components and the embedded software. Different embedded software types will lead to different arrangements of hardware executions and different system reliability quantities. In this paper, we propose a novel probabilistic model, called the hybrid relation model (HRM), for the reliability analysis of PLC systems. Its construction is based upon the execution logic of the embedded software and the distribution of the hardware components. We prove the constructed HRM to be a Bayesian network (BN) that captures the execution logic of the embedded software. Then, we map the hardware components to the corresponding HRM nodes and embed the failure probabilities of the hardware components into the well-defined conditional probability distribution tables of the HRM nodes. With the computational mechanism of the BN, the HRM handles the failure probabilities of the hardware components as well as the complex relations caused by the execution logic of the embedded software. Experiment results demonstrate the accuracy of our model.

Bi-Directional Synthesis of 4-Bit Reversible Circuits

Reversible circuits play an important role in quantum computing, which is one of the most promising emerging technologies. In this paper, we investigate the problem of optimally synthesizing 4-bit reversible circuits. We present an enhanced bi-directional synthesis approach. Owing to the exponential nature of the memory and run-time complexity, all existing methods can only perform four steps for the Controlled-Not gate NOT gate, and Peres gate library. Our novel method can achieve 12 steps. As a result, we augment the number of circuits that can optimally be synthesized by over 5 × 106 times. We synthesized 1000 random 4-bit reversible circuits. The statistical analysis result supports our estimation. The quantum cost of our result is also better than the quantum cost of other approaches. The promising experimental results demonstrate the effectiveness of our approach.

Board-level multiterminal net assignment for the partial cross-bar architecture

This paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in the digital design of clos-folded field-programmable gate array (FPGA) based logic emulation systems. The approach transforms the FPGA board-level routing task into a Boolean equation. Any assignment of input variables that satisfies the equation specifies a valid routing. We use two of the fastest Boolean satisfiability (SAT) solvers: Chaff and DLMSAT to perform our experiments. Empirical results show that the method is time-efficient and applicable to large layout problem instances.

BDD variable ordering by scatter search

Reduced ordered binary decision diagrams (BDDs) are a data structure for representation and manipulation of Boolean functions which are frequently used in VLSI design automation. The variable ordering largely influences the size of the BDD, varying from linear to exponential. In this paper we study BDD minimization problem based on scatter search optimization. The results we obtained are very encouraging in comparison with other heuristics (genetic and simulated annealing). This work is the first successful experience of using scatter search approach in design automation area. The approach can be applied to many design automation applications.