LeRoy Winemberg

Design and Analysis of a Delay Sensor Applicable to Process/Environmental Variations and Aging Measurements

With technology scaling, the deviation between predicted path delay using simulation and actual path delay on silicon increases due to process variation and aging. Hence, on-chip measurement architectures are now widely used due to their higher accuracy and lower cost compared to using external expensive measurement devices. In this paper, a novel path-delay measurement architecture called path-based ring oscillator (Path-RO) which takes into account variations is proposed. Path-RO can perform accurate on-chip path-delay measurement with nearly no impact on functional data path. At the same time, process variations will not affect the measurement accuracy. The accuracy degradation due to aging is also negligible, which enables Path-RO to monitor path delay throughout aging process. This delay sensor is perfectly suitable for fast and accurate speed binning as well. By targeting speed paths, the speed of chip can be binned efficiently even in presence of clock skew. Various simulation results collected by Path-RO inserted into b19 circuit demonstrate its high accuracy and efficiency.

Screening customer returns with multivariate test analysis

This work studies the potential of capturing customer returns with models constructed based on multivariate analysis of parametric wafer sort test measurements. In such an analysis, subsets of tests are selected to build models for making pass/fail decisions. Two approaches are considered. A preemptive approach selects correlated tests to construct multivariate test models to screen out outliers. This approach does not rely on known customer returns. In contrast, a reactive approach selects tests relevant to a given customer return and builds an outlier model specific to the return. This model is applied to capture future parts similar to the return. The study is based on test data collected over roughly 16 months of production for a high-quality SoC sold to the automotive market. The data consists of 62 customer returns belonging to 52 lots. The study shows that each approach can capture returns not captured by the other. With both approaches, the study shows that multivariate test analysis can have a significant impact on reducing customer return rates especially during the later period of the production.

Important test selection for screening potential customer returns

In a market where quality requirements are extremely high; the ultimate goal is to improve test quality and reduce the occurrence of test escapes. A customer return is a test escape which passes all tests but fails in the field. This paper analyzes seven lots of parametric wafer probe test data, where each lot contains one customer return. We ask a fundamental question: What subset of tests provides the best screening of customer returns? This leads us to the problem of selecting sets of important tests which contain necessary information to identify each customer return. We compare and combine three test selection methods and suggest an outlier analysis based test strategy for screening potential customer returns.

Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits

This work proposes a wafer probe parametric test set optimization method for predicting dies which are likely to fail in the field based on known in-field or final test fails. Large volumes of wafer probe data across 5 lots and hundreds of parametric measurements are optimized to find test sets that help predict actually observed test escapes and final test failures. Simple rules are generated to explain how test limits can be tightened in wafer probe to prevent test escapes and final test fails with minimal overkill. The proposed method is evaluated on wafer probe data from a current automotive IC with near zero DPPM requirements resulting in improved test quality and reduced test cost.

Fault analysis and simulation of large scale industrial mixed-signal circuits

High test quality can be achieved through defect oriented testing using analog fault modeling approach. However, this approach is computationally demanding and typically hard to apply to large scale circuits. In this work, we use an improved inductive fault analysis approach to locate potential faults at layout level and calculate the relative probability of each fault. Our proposed method yields actionable results such as fault coverage of each test, potential faults, and probability of each fault. We show that the computational requirement can be significantly reduced by incorporating fault probabilities. These results can be used to improve fault coverage or to improve defect resilience of the circuit.

In-field aging measurement and calibration for power-performance optimization

Aging of transistors has become a major reliability concern especially when the VLSI circuits are in the nanometer regime. In this paper, we propose a novel methodology to address circuit aging in the field. On-chip aging sensor is designed to monitor transitions on functional paths capturing functional mode workload. Path delay is then accurately measured and converted to a digital value. Diagnosis and calibration are performed in the field, thereby achieving power-performance optimization throughout the entire lifetime. Simulation results demonstrate the efficiency of the proposed structure.

A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs

Because of process variations, the post-silicon critical or near-critical paths differ from those identified in the pre-silicon stage. Thus, it has become necessary to extract timing slack information from circuit paths in the post-silicon phase. In this paper, we present a robust digital sensor IP for in-situ timing slack monitoring on actual circuit paths from SoCs. The timing slack data is converted into a digital format and stored in a dedicated scan register chain for easy extraction at any point in time during test and functional modes. A novel layout-aware and netlist-level sensor insertion flow is proposed. The sensor IP has been designed with 32/28nm standard cell library and its performance is demonstrated in the physical design of several benchmark circuits.

Understanding customer returns from a test perspective

Customer returns are defective parts that pass all functional and parametric tests, but fail in the field. To prevent customer returns, this paper analyzes wafer probe test data and tries to understand what it takes to screen them out during testing. Because these parts pass all tests, analyzing their signatures based on the original test perspective does not make sense. In this work, we search for a novel test perspective where the test signatures from parametric measurements can be used to separate the returned parts from the rest of population. Our study shows that in order to effectively screen customer returns during wafer test, a multivariate screening methodology is desired. This study is based on analyzing over 1000 parametric wafer probe tests and dies from seven lots, each lot containing one returned part. We demonstrate that analyzing customer returns from a multivariate test perspective leads to robust and conservative results.

Forward prediction based on wafer sort data — A case study

This paper studies the potential of using wafer probe tests to predict the outcome of future tests. The study is carried out using test data based on an SoC design for the automotive market. Given a set of known failing parts, there are two possible approaches to learn. First a single binary classification model can be learned to model all failing parts. We show that this approach can be effective if the failing parts are compatible in learning. Second, an individual outlier model can be learned for each failing part. We show that this approach is suitable for learning failing parts such as customer returns, where each may have a unique failing behavior. We also show that with Principal Component Analysis (PCA), a learning model can be visualized in two or three dimensional PC space, which facilitates an engineer to manually select or adjust the model.

A Novel Peak Power Supply Noise Measurement and Adaptation System for Integrated Circuits

For 45-nm technologies and below, the maximum operation frequency of integrated circuits (ICs) has reached multiple gigahertz. At the same time, the size of modern ICs has increased significantly with several billions of transistors integrated on each die. When a large number of transistors switch at the same time, high current consumption is generated. The high current consumption combining with the parasitic resistance and inductance of the power supply network generates a significant power supply noise peak, which causes abnormal reset and generates excessive radiation emission, and hence needs to be accurately monitored, adapted, and mitigated. This paper presents a novel power supply noise measurement and adaptation system that can monitor the peak power supply noise and make dynamic adaptation within one clock cycle. The proposed system has been implemented in Nangate 45-nm technology. It has been proved that the proposed measurement and the adaptation system can successfully avoid the performance degradation or functional failure due to excessive power supply noise. The peak power supply noise monitoring accuracy is 5 mV. The adaptation reaction time is 75%-100% of single system clock cycle. The proposed system is robust against temperature and process variation, and of negligible area overhead and power consumption.