Dragoljub Gagi Drmanac

Predicting variability in nanoscale lithography processes

As lithography process nodes shrink to sub-wavelength levels generating acceptable layout patterns becomes a challenging problem. Traditionally, complex convolution based lithography simulations are used to estimate areas of high variability. These methods are slow and infeasible for large scale full chip analysis. This work proposes a solution to this problem by using machine learning techniques to identify layout areas that are more prone to variability. A novel target layout representation is proposed, and the latest support vector machine (SVM) algorithms are used to detect variability within standard cells and between cells in a simulated full chip layout.

A Study of Outlier Analysis Techniques for Delay Testing

This work provides a survey study of several outlier analysis techniques and compares their effectiveness in the context of delay testing. Three different approaches are studied, an Euclidean-distance based algorithm, random forest, and one-class support vector machine (SVM), from which more advanced methods are derived and analyzed. We conclude that one-class SVM using a polynomial kernel is most effective for detecting delay defects, while keeping overkills minimized. The best models were successfully validated and a feasible approach to delay testing using one-class SVM is proposed.

Important test selection for screening potential customer returns

In a market where quality requirements are extremely high; the ultimate goal is to improve test quality and reduce the occurrence of test escapes. A customer return is a test escape which passes all tests but fails in the field. This paper analyzes seven lots of parametric wafer probe test data, where each lot contains one customer return. We ask a fundamental question: What subset of tests provides the best screening of customer returns? This leads us to the problem of selecting sets of important tests which contain necessary information to identify each customer return. We compare and combine three test selection methods and suggest an outlier analysis based test strategy for screening potential customer returns.

Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits

This work proposes a wafer probe parametric test set optimization method for predicting dies which are likely to fail in the field based on known in-field or final test fails. Large volumes of wafer probe data across 5 lots and hundreds of parametric measurements are optimized to find test sets that help predict actually observed test escapes and final test failures. Simple rules are generated to explain how test limits can be tightened in wafer probe to prevent test escapes and final test fails with minimal overkill. The proposed method is evaluated on wafer probe data from a current automotive IC with near zero DPPM requirements resulting in improved test quality and reduced test cost.

Minimizing outlier delay test cost in the presence of systematic variability

This work proposes a methodology to minimize the application cost of outlier analysis when applied to delay testing in the presence of systematic variability. Support vector machine (SVM) outlier analysis algorithms and traditional entropy measures are used to detect delay defects by choosing a minimum number of suitable test clocks. Monte Carlo simulations generate realistic test data while information content measurements guide test clock selection. Exhaustive simulation found trade-offs between reducing the number of clocks, patterns, and chip samples. Substantial cost reduction was obtained with proper clock selection, while minimizing both test patterns and circuit samples required for effective outlier analysis.

Mining AC delay measurements for understanding speed-limiting paths

Speed-limiting paths are critical paths that limit the performance of one or more silicon chips. This paper present a data mining methodology for analyzing speed-limiting paths extracted from AC delay test measurements. Based on data collected on 15 packaged silicon units of a four-core microprocessor design, we show that the proposed methodology can efficiently discovered actionable, design-related knowledge that would be difficult to find otherwise.

Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch

Due to the magnitude and complexity of design and manufacturing processes, it is unrealistic to expect that models and simulations can predict all aspects of silicon behavior accurately. When unexpected behavior is observed in the post-silicon stage, one desires to identify the causes and consequently identify the fixes. This paper studies one formulation of the design-silicon mismatch problem. To analyze unexpected behavior, silicon behavior is partitioned into two classes, one class containing instances of unexpected behavior and the other with rest of the population. Classification rule learning is applied to extract rules to explain why certain class of behavior occurs. We present a rule learning algorithm that analyzes test measurement data in terms of design features to generate rules, and conduct controlled experiments to demonstrate the effectiveness of the proposed approach. Results show that the proposed learning approach can effectively uncover rules responsible for the design-silicon mismatch even when significant noises are associated with both the measurement data and the class partitioning results for capturing the unexpected behavior.

Understanding customer returns from a test perspective

Customer returns are defective parts that pass all functional and parametric tests, but fail in the field. To prevent customer returns, this paper analyzes wafer probe test data and tries to understand what it takes to screen them out during testing. Because these parts pass all tests, analyzing their signatures based on the original test perspective does not make sense. In this work, we search for a novel test perspective where the test signatures from parametric measurements can be used to separate the returned parts from the rest of population. Our study shows that in order to effectively screen customer returns during wafer test, a multivariate screening methodology is desired. This study is based on analyzing over 1000 parametric wafer probe tests and dies from seven lots, each lot containing one returned part. We demonstrate that analyzing customer returns from a multivariate test perspective leads to robust and conservative results.

Online selection of effective functional test programs based on novelty detection

This paper proposes an online functional test selection approach based on novelty detection. Unlike other test selection methods, the idea of this paper is selecting novel functional tests to improve coverage from a large pool of available test programs before simulation. A graph based encoding scheme is developed to measure the similarity between test programs and map them into a set of feature vectors. We employ one-class SVM as the learning algorithm to detect novel tests to be simulated. While leaving the general test selection framework unchanged, the developed test program similarity measure can easily be tailored to specific applications and coverage targets based on existing simulation results. Experiments on a public domain MIPS processor design are presented to demonstrate the effectiveness of the approach.

Wafer probe test cost reduction of an RF/A device by automatic testset minimization — A case study

This work presents a case study of wafer probe test cost reduction by multivariate parametric testset optimization for a production RF/A device. More than 1.5 million tested device samples across dozens lots and hundreds of parametric measurements are analyzed using a new automatic testset minimization system. Parametric test subsets are found that can be used to predict infrequent wafer probe failures. Multivariate test models are generated to justify removal of ineffective tests, screen failures with minimal test cost, and demonstrate that some frequently passing tests are safe drop candidates. The proposed method is evaluated using parametric test data from an RF/A IC currently in production, showing how to reduce test cost and uncover tradeoffs between test escapes and overkills during high volume wafer probe screening.