Michael B. Henry

NEMS-Based Functional Unit Power-Gating: Design, Analysis, and Optimization

In order to combat the exponentially growing leakage power in modern microprocessors, researchers have proposed the use of alternative power-gating structures that can yield higher leakage savings with a much lower performance impact. A prime contender is an emerging CMOS-compatible power-gating device, the nanoelectromechanical systems (NEMS) switch. Compared to transistors, NEMS switches have zero off-state leakage, so for very long periods of sleep, their effectiveness is unparalleled. For systems with periods of faster on/off rates, however, their slower switching speed, high activation energy, and finite device lifetime become drawbacks. This motivates an exploration to determine whether NEMS switches are capable of fast, fine-grained power-gating. In this article, we provide an accurate energy model of functional-unit power-gating that allows us to effectively compare transistors and NEMS switches. It is also fast enough to support the optimization of a wide variety of circuit- and system-level parameters, including supply voltage, threshold voltage, and power-gating scheduler aggressiveness. Using this framework, we show that NEMS switch power-gates along with an ideal oracle power-gating policy can achieve an average 29.5% drop in total functional unit energy, compared to only 23.5% with transistor power-gates. A more realistic hardware-based policy for NEMS switches yields a 28.9% drop, compared to a 23.0% drop with transistors.

From transistors to MEMS: throughput-aware power gating in CMOS circuits

In this paper we study the effectiveness of two power gating methods - transistor switches and MEMS switches - in reducing the power consumption of a design with a certain target throughput. Transistor switches are simple, but have fundamental limitations in their effectiveness. MEMS switches, with zero leakage in the off state, have achieved much focus over the past decade in the RF field, but have only very recently been explored in the context of power gating. In this paper we study both methods in conjunction with voltage scaling and show that MEMS switches are the superior choice over a wide range of target throughputs, especially low-throughput applications such as wireless sensor networks and biomedical implants. We also show that the architectural choices and operating conditions in a throughput-aware design can be profoundly different when using MEMS switches as opposed to transistor switches. For instance, while transistor switches favor smaller and slower architectures, the MEMS switches favor larger and faster designs when the target throughput is low. Moreover, while the optimal operating voltage of a transistor-switched design resides in the subthreshold region, that of a MEMS-switched design can be above or near the threshold voltage. To prove this, we provide both a mathematical analysis and experimental results from four different FFT architectures.

ASIC implementations of five SHA-3 finalists

Throughout the NIST SHA-3 competition, in relative order of importance, NIST considered the security, cost, and algorithm and implementation characteristics of a candidate [1]. Within the limited one-year security evaluation period for the five SHA-3 finalists, the cost and performance evaluation may put more weight in the selection of winner. This work contributes to the SHA-3 hardware evaluation by providing timely cost and performance results on the first SHA-3 ASIC in 0.13 μm IBM process using standard cell CMOS technology with measurements of all the five finalists using the latest Round 3 tweaks. This article describes the SHA-3 ASIC design from VLSI architecture implementation to the silicon realization.

Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture

In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that turns the transistors on and off. Even though the transistors are not actually switching as usual in this region, they are able to complete the computation by modulating the leakage current that passes through them, resulting in a 20-100x decrease in power consumption. Our hybrid FFT design partitions a sequential butterfly FFT architecture into two regions, namely memory banks and processing elements, such that the former runs in the superthreshold region and the latter in the subthreshold region. For a given throughput, the number of parallel processing units and their supply voltage is determined such that the overall power consumption of the design is minimized. For a 1024 point FFT operation, our parallel design is able to deliver the same throughput as a serial design, while consuming 70% less power. We study the effectiveness of this method for a variable throughput application such as a sensor node switching between a low throughput and high throughput mode, e.g. when sensing an interesting event. We compare our method with other methods used for throughput scaling such as voltage scaling and clock scaling and find that our scaling method will last up to three times longer on battery power. We also analyze the trade-offs involved in our method, including yield and device size issues.

Design and benchmarking of an ASIC with five SHA-3 finalist candidates

This contribution describes our efforts in the design of a 130nm CMOS ASIC that implements Skein, BLAKE, JH, Grostl, and Keccak, the five candidates selected by NIST in the third round SHA-3 competition. The objective of the ASIC is to accurately measure the performance and power dissipation of each candidate when implemented as an ASIC. The design of this ASIC, and its optimization for benchmarking, creates unique problems, related to the integration of five heterogeneous architectures on a single chip. We implemented each algorithm in a separate clock region, and we integrated an on-chip clock generator with flexible testing modes. The chip is further designed to be compatible with SASEBO-R board, a power-analysis and side-channel analysis environment. We report the design flow and test results of the chip, including area, performance and shmoo plot. Furthermore, we compare our ASIC benchmark with an equivalent FPGA benchmark.

Pre-silicon Characterization of NIST SHA-3 Final Round Candidates

The NIST SHA-3 competition aims to select a new secure hash standard. Hardware implementation quality is an important factor in evaluating the SHA-3 finalists. However, a comprehensive methodology to benchmark five final round SHA-3 candidates in ASIC is challenging. Many factors need to be considered, including application scenarios, target technologies and optimization goals. This work describes detailed steps in the silicon implementation of a SHA-3 ASIC. The plan of ASIC prototyping with all the SHA-3 finalists, as an integral part of our SHA-3 ASIC evaluation project, is motivated by our previously proposed methodology, which defines a consistent and systematic approach to move a SHA-3 hardware benchmark process from FPGA prototyping to ASIC implementation. We have designed the remaining five SHA-3 candidates in 0.13

Fast simulation framework for subthreshold circuits

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A low-power parallel design of discrete wavelet transform using subthreshold voltage technology

IBM process using standard-cell CMOS technology. In this paper, we discuss our proposed methodology for SHA-3 ASIC evaluation and report the latest results based on post-layout simulation of the five SHA-3 finalists with Round 3 tweaks.

Design of energy-efficient, adaptable throughput systems at near/sub-threshold voltage

Subthreshold voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. This is beneficial in embedded applications that must run off of batteries and scavenged energy. Subthreshold operation has been proven to be very effective by several successful prototypes in the recent years, yet there is no fast and effective way for designers to estimate power and delay of a design operating in the subthreshold region. Traditional gate-level simulation tools are not set up to perform timing and power analysis in the subthreshold region and transistor level simulations are very time consuming due to the accuracy required to measure the very low levels of current. This paper presents a simulation framework that can accurately characterize a circuit from nominal voltage, all the way down into the subthreshold region. This framework uses the nominal frequency and power of a target circuit and a normalized ring oscillator curve to characterize the circuit at lower voltages. The contribution of this paper is a detailed analysis of this framework in the presence of a variety of design parameters such as bus lengths, transistor widths, etc. The simulation framework is extremely quick and accurate across a wide variety of circuits.

Design of low-power, scalable-throughput systems at near/sub threshold voltage

The Discrete Wavelet Transform (DWT) is a means to analyze the frequency content of a signal and has extensive uses, including the JPEG2000 codec. Many portable and battery operated applications of DWT are expected in the near future that require a low power implementation of this transform. In this paper, a parallel VLSI implementation of a 2D lifting-based DWT processor is presented that is scalable from 2 to 256 parallel units. This design benefits from an efficient data distribution module to the parallel units, which constitutes a small overhead, and is able to significantly benefit from voltage scaling to achieve energy efficiency. In our design, the number of parallel units is increased and their speed is reduced through voltage scaling, while maintaining a constant throughput. Our results show that the optimal operating voltage of the parallel units, for a target throughput of 200MHz,4 is 386mV. This is below the threshold voltage, which is the voltage that turns the transistors on. Since operating a circuit in subthreshold voltage consumes 100+ times less power than running it at nominal voltage, our design is able to provide the same throughput as a reference pipelined implementation with 26 times less power consumption.