Li-Ming Denq

SOC Test Architecture and Method for 3-D ICs

3-D integration provides another way to put more devices in a smaller footprint. However, it also introduces new challenges in testing. Flexible test architecture named test access control system for 3-D integrated circuits (TACS-3D) is proposed for 3-D integrated circuits (IC) testing. Integration of heterogeneous design-for-testability methods for logic, memory, and through-silicon via (TSV) testing further reduces the usage of test pins and TSVs. To highly reuse pre-bond test circuits in post-bond test, an innovative linking mechanism shares TSVs and test pins of the 3-D IC. No matter how many layers are there in the 3-D IC, a large portion of TSVs and test pins is reserved for data application. Therefore, smaller post-bond test time is expected. A test chip composed of a network security processor platform is taken as an example. Less than 0.4% test overhead increases in area and time between 2-D and 3-D cases. Compared with the instinctively direct access, TACS-3D reveals up to 54% test time improvement under the same TSV usage.

A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories

It is common that an SOC contains hundreds or even thousands of heterogeneous embedded memories. Many of these embedded memories have wide data words, leading to high routing penalty from the BIST circuits. Previous BIST schemes solve the problem using serial interface, e.g., based on the IEEE 1500 architecture and novel scan approaches, to reduce the routing area overhead. However, serial approaches do not allow at-speed test and diagnosis, and are very slow. In this paper, we propose a hybrid BIST architecture that reduces the routing penalty, while allowing at-speed test and diagnosis of the memory cores. The test time is close to that of a typical parallel BIST method. Experimental results show that the proposed BIST can effectively reduce the area overhead.

An Enhanced SRAM BISR Design with Reduced Timing Penalty

Redundancy repair is an effective yield-enhancement technique for memories. There are many previously proposed repair methodologies, such as the popular repair methodology based on the concept of address remapping mechanism achieved by address comparison and address reconfiguration. However, a BISR design with a typical address remapping mechanism usually involves significant timing penalty. Therefore, we propose a new address remapping scheme with a write buffer to reduce the timing penalty. Our experiments show that with the proposed address remapping scheme and redundancy architecture, the timing penalty of our BISR scheme is the same with that of the built-in self-test (BIST) circuit-only one multiplexer delay for both the inputs and outputs

3D-IC BISR for stacked memories using cross-die spares

3D ICs based on Through-Silicon-Vias (TSVs) enable the stacking of logic and memory dies to manufacture chips with higher performance, lower power, and smaller form factor. To improve the yield of the memory dies in 3D ICs, this paper proposes a Built-In Self-Repair (BISR) architecture which allows the sharing of spares between different layers of dies. The corresponding pre-bond (before the memory dies are bonded together) and post-bond (after the memory dies are bonded together) test flow is presented as well. In order to maximize the yield gain introduced by the cross-die spares, a die matching algorithm is proposed to determine which dies should be stacked together, so that the spare sharing can be most efficient. Experimental results show that the area overhead of the proposed BISR circuit is only 2.43%, which can be smaller if larger logic and memory dies are adopted, and the yield gain achieved by cross-die spare sharing can be up to 23%.

Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories

Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cells defect information. A failure bitmap viewer provides visual information for design and process diagnostics.

An SOC test integration platform and its industrial realization

One of the major costs in system-on-chip (SOC) development is test cost, especially the cost related to test integration. Although there have been plenty of research works on individual topics about SOC testing, few of them took into account the practical integration issues. In this paper, we stress the practical SOC test integration issues, including real problems found in test scheduling, test IO reduction, timing of functional test, scan IO sharing, etc. A test scheduling method is proposed based on our test architecture and test access mechanism (TAM), considering IO resource constraints. Detailed scheduling further reduces the overall test time of the system chip. We also present a test wrapper architecture that supports the coexistence of scan test and functional test. The test integration platform has been applied to an industrial SOC case. The chip has been designed and fabricated. The measurement results justify the approach-simple and efficient, i.e., short test integration cost, short test time, and small area overhead.

Economic Analysis of the HOY Wireless Test Methodology

The HOY (Hypothesis, Odyssey, and Yield) test system provides wireless test access and embedded DFT, while offering lower cost and better performance than conventional ATE. This article briefly describes HOY, then proposes a test cost model to compare it with conventional ATE, and analyzes the test cost of these two methods for different manufacturing processes, area overheads, die sizes, manufacturing volumes, and test times.

A parallel built-in diagnostic scheme for multiple embedded memories

Hundreds of memory cores can be found on a typical system-on-chip (SOC) today. Diagnosing such a large number of memory cores using a conventional built-in self-test (BIST) architecture consumes too much time, as its on-chip diagnostics support is for sequential diagnosis only. In this paper, we present a memory BIST architecture with parallel diagnosis scheme. The proposed parallel built-in self-diagnosis (PBISD) scheme was developed to work with our existing memory optimization and reconfiguration (MORE) system, which configures small memory cores into the large one specified by the user, subject to the power and geometry constraints. With PBISD and MORE, memory test and diagnosis can be done in a much shorter time, and the whole system provides a good balance among test time, test power, and test hardware overhead. Experimental results show that, when compared with a conventional BISD scheme, the diagnosis time for a case with four memory cores is only 25%. Moreover, the area overhead is only 49%, as only one test pattern generator is required.

A testability-driven optimizer and wrapper generator for embedded memories

Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation-a large memory may need to be implemented with multiple small memories, if generated by memory compilers. In this paper we introduce a testability-driven memory optimizer and wrapper generator that generates BISTed embedded memories by using a commercial memory compiler. We describe one of its key components called MORE (for Memory Optimization and REconfiguration). The approach is cost effective for designing embedded memories. By configuring small memory cores into the large one specified by the user and providing the BIST circuits, MORE allows the user to combine the commercial memory compiler and our memory BIST compiler into a cost-effective testability-driven memory generator. The resulting memory has a shorter test time, since the small memory cores can be tested in parallel, so far as the power and geometry constraints are considered. As an example, the test time of a typical 256 K/spl times/32 memory generated by MORE is reduced by about 75%.

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing

This work presents a low-cost wireless system design that serves as an interface to support the SoC with contactless testability feature. The communication hierarchy includes PHY, MAC, data exchange, and test wrapper functions. The wireless does not require external antennae and crystal reference, and therefore minimize the setup cost. The embedded all-digital timing generation achieves robust performance in the noisy environment. The whole wireless system occupies a small area. In a 0.18µm device-under-test, the active area of wireless front-end is 0.14mm2 and the gate count for digital processing is 112K. The maximum energy efficiency for uplink is 1.1nJ/bit and for downlink is 2.9nJ/bit when the wireless distance is set around 1cm. The prototype system includes test equipment and an SoC as the device-under-test. The SoC integrating logic, memory, and analog plug-in modules can be contactlessly tested. It is a low-cost platform controlled by a simple hand-held computer.