Li-Shian Jeng

New Negative-Bias-Temperature-Instability Improvement Using Buffer Layer under Highly Compressive Contact Etch Stop Layer for 45-nm-Node Complementary Metal–Oxide–Semiconductor and Beyond

A remarkable 50% drive current enhancement for p-type metal–oxide–semiconductor field-effect-transistors (pMOSFETs) using a highly compressive SiN contact etch stop layer (CESL) has been successfully demonstrated. In this study, we also first proposed that applying a modulated buffer layer prior to the highly compressive CESL could significantly improving negative-bias-temperature-instability (NBTI) and time-dependent-dielectric-breakdown (TDDB) degradation of pMOSFETs using compressive CESL. Without adversely impact the significant drive current enhancement of pMOSFETs, this thin modulated buffer layer can improve the NBTI lifetime of core pMOSFETs by over two orders of magnitude. Instead of the complex and high-costly SiGe refill scheme, this highly compressive CESL layer with a thin modulated buffer layer successfully demonstrates a better candidate for pMOSFETs drive current enhancement of 45-nm-node CMOS and beyond.

56% pMOSFETs Drive Current Enhancement from Optimized Compressive Contact Etching Stop Layer (CESL) for 45nm Node CMOS

With further optimizing the conventional compressive CESL, the record 56% drive current gain of pMOSFETs has been first demonstrated instead of high cost and complex SiGe process. Compared to conventional compressive CESL performance, this optimized film also provides an extra 24% current gain on pMOSFETs, which far derivates from the trend of the drive current gain on the integrated film stress. Introduction As downscaling the CMOS device dimension reaches its fundamental limits, the enhancement of carrier mobility has been widely researched by introducing strain technology into the channel region. The local strain techniques by using tensile and compressive nitride CESL (Contact-Etch-Stop-Layer) films were introduced to improve electron mobility for nMOSFETs and hole mobility for pMOSFETs, respectively [1-4]. To achieve a higher drive current of pMOSFETs, most studies were also focused on S/D SiGe refill technologies [5,6], but the SiGe scheme suffers from more challenges including complex integration, process control and high cost. In this study, we addressed on the development of much higher compressive CESL for easier integrated capability. By the breakthrough on the C_CESL (Compressive CESL) modification, higher strain could be more effectively transferred into the channel of pMOSFETs and the record 56% drive current gain can be also reached, competed to the performance of the SiGe scheme. Various electrical, capacitance and reliability characteristics were measured to prove this optimized C_CESL applicability. Device Preparation Process flow for the CMOS device is shown in Fig.1. The high performance device was fabricated on a <110> P-type substrate. Shallow trench isolation was applied to define device active area and prevent leakage current. Then well and Vt implantations were followed to define the channel profile. After a triple-oxynitride gate process, the poly line was patterned and the transistors were optimized with shallow extensions and S/D RTA. After NiSi process, a compressive nitride CESL film was introduced to enhance the channel strain of pMOSFETs. Control wafers were deposited by conventional nitride CESL film with very low stress. Fig. 2 shows a cross-section TEM picture of the pMOSFETs device. Results and Discussion The normalized drive current (Ion) vs. off current (Ioff) characteristics of the short-channel pMOSFETs has been further enhanced by the presence of an optimized C_CESL layer, as shown in Fig. 3. 56% drive current gain is already observed by optimizing the C_CESL, while only 32% drive current gain can be achieved by the conventional C_CESL. The optimized C_CESL film transfers a higher stress into the channel of pMOSFETs and demonstrates an excellent drive current gain. Compared to recent SiGe improvement activities [4-6] listed in Table 1, this work shows a competitive drive current gain of pMOSFETs. Besides, this maximum current gain can be achieved only by optimizing C_CESL film deposition without developing new material. Instead of complex integration and huge extra cost by SiGe technology, the optimized C_CESL film becomes the better candidate for pMOSFETs’ drive current enhancement. Fig. 4 shows the dependence of the drive current gain on the integrated film stress for pMOSFETs and higher saturated drive current gain could be obtained by the optimized C_CESL. As the integrated film stress increased over a specific stress, the drive current gain significantly derivates from the liner trend (Fig. 5) and the slop speeds up into a superior linear behavior. It is consistent with the previous report [7] that an extreme compressive stress can modulate the bandstructure resulting in more significant hole mobility enhancement with lower hole effective mass and scattering suppression. Fig. 6 and 7 show the Id-Vgs and Id-Vds curves of pMOSFETs with Lpoly=38nm, respectively. The swing values of control wafer, conventional C_CESL and optimized C_CESL devices are around 96mV/decade. The comparable Vt roll-off and the DIBL (Drain-Induced-BarrierLowering) characteristics are also shown in Fig. 8 and Fig. 9, respectively. In Fig. 10, the Gm gain gap of the optimized C_CESL (+140%) is much better than that of the conventional C_CESL (+70%) by a factor of 2. It is believed that the channel hole mobility could be further enhanced successfully by the optimized C_CESL. C-V (Capacitance-Voltage) characteristics shown in Fig. 11 are comparable between different C_CESL film and the control wafers. The results indicated that the process with the optimized C_CESL layer would not induce extra charges trapping in the oxide bulk. Fig. 12 shows the Ion-Ioff characteristics of the test structures with and without dummy poly pattern. Up to 72% drive current gain of pMOSFETs without dummy poly pattern could be obtained by the optimized C_CESL. It is explained that the stress would be suppressed by the dummy poly pattern. Fig.13 shows a TCAD simulation on dummy poly effect where the dummy poly space is defined from 0.2um to 1.4um. The simulation shows the 9.3% degradation of Sxx (longitudinal way) stress is observed from space=1.4um to 0.3um. That clarifies the current gain offset between the test structures with and without dummy poly pattern. Furthermore, once the space narrower than 0.3um, it will be degraded rapidly to 40% loss as space=0.2um. Thus, the dummy poly pattern also plays an important role in the optimization of the integrated film stress. Finally, in Fig. 14, the NBTI of IO pMOSFETs was also stressed at Vg=-4.4V and 125C. Results show that NBTI degradation for the optimized C_CESL film still keeps the same to the control wafers and traditional C_CESL. Conclusions With optimizing C_CESL, the drive current gain of 56% has been successfully demonstrated for 45nm node CMOS, and is extendible to future technologies. In this study, the CESL scheme has proved to be the superior and friendly candidate instead of high cost and complex SiGe process. Compared to conventional compressive CESL performance, this optimized film can also provide an extra 24% current gain on pMOSFETs, which far derivates from the trend of the drive current gain on the integrated film stress. References [1] C. W. Liu, et al., IEEE Circuit & Device Magazine, p. 21, 2005 [2] C. D. Sheraw, et al., Symp. On VLSI Tech., p. 12, 2005 [3] C.H. Ko, et al., IEEE VLSI-TSA Int. Symp., p. 25, 2005 [4] H.S. Yang, et al., IEDM Tech. Dig., p. 1075, 2004 [5] P. Bai, et al., IEDM Tech. Dig., p. 657, 2004 [6] M. Horstmann, et al., IEDM Tech. Dig.,p. 243, 2005 [7] E. Wang, et al., IEDM Tech. Dig.,p. 147, 2004 Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, Yokohama, 2006, -178H-2-5 pp. 178-179

NBTI Improvement under Highly Compressive Contact Etching Stop Layer (CESL) for 45nm Node CMOS and Beyond

Instead of the complex and high cost SiGe refill scheme, up to 50% drive current enhancement of pMOSFETs has been successfully demonstrated by a highly compressive SiN contact etch stop layer (CESL). Unfortunately, NBTI and TDDB would be degraded due to higher hydrogen from the CESL. In this study, we first proposed that upon application of a modulated buffer layer prior to a highly compressive CESL deposition, the hydrogen could be effectively screened and NBTI and TDDB were also significantly improved without adverse impact on the current enhancement for pMOSFETs. Moreover, the NBTI lifetime for core pMOSFETs could be remarkably improved by over two orders of magnitude. Introduction To extend CMOS physical limit, local strain techniques with tensile and compressive nitride CESL layers have been introduced to improve electron mobility and hole mobility, respectively, in the channel region [1-3]. However, most previous literatures focused on the benefits of mobility enhancement on core devices, while much less work was aimed at investigating device reliability. Unfortunately, worse NBTI and TDDB have also been observed after a highly compressive nitride CESL was applied to achieve mobility enhancement in the pMOSFETs’ channel [4-7]. It has been reported [7,8] that the physical mechanism of reliability degradation is due to higher content of Si-H and N-H bonds from the compressive nitride CESL film [7]. How to overcome the barrier becomes a challenge for 45nm node CMOS and beyond. In this study, 50% drive current gain of pMOSFETs has been achieved by optimizing the SiN compressive CESL. However, we addressed a modulated buffer layer with low thermal budget (<450C), used as a buffer layer to substantially suppress hydrogen incorporation from the highly compressive nitride CESL film. Results reveal that good NBTI and TDDB for pMOSFETs were obtained and the NBTI lifetime could be improved by over two orders of magnitude without adverse impact on the current enhancement of pMOSFETs. Device Preparation A high performance CMOS device was fabricated with a dual-oxynitride gate process of 58Å and 12Å physical thickness. After gate patterning, the transistors were integrated with shallow extensions and S/D implants, followed by a rapid thermal anneal. A highly compressive nitride CESL was introduced to enhance the channel strain for pMOSFETs. Before the highly compressive nitride CESL was deposited, on the other hand, a thin modulated buffer layer with low thermal budget below 450C was first applied to improve the reliability of NBTI and TDDB for pMOSFETs. With the thin modulated buffer layer, there was no adverse impact on the channel strain. Figure 1 shows a TEM cross-section of pMOSFETs with a modulated buffer layer. Results and Discussion I. Transistor Characteristics Instead of the high cost and complex SiGe refill scheme, up to 50% drive current enhancement of pMOSFETs has been successfully demonstrated by introducing a highly compressive CESL (Fig. 2). The results indicate that the high stress CESL is still appropriate for 45nm node CMOS and beyond. As an enough thin buffer layer-A was first introduced prior to the CESL film deposition, there was no adverse impact on the drive current enhancement for pMOSFETs, shown in Fig. 3(a). The drive current gains with different compressive CESL thickness as a function of buffer layer thickness are described in Fig. 3(b). Less performance enhancement of core pMOSFETs has been observed as the thickness of the buffer layer was increased above a critical thickness-B. For IO pMOSFETs, the electrical characteristics Id-Vd are shown in Fig. 4 and the current enhancement with a highly compressive CESL was insensitive to the buffer layer thickness. Fig. 5 illustrates C-V characteristics for IO pMOSFETs with and without a buffer layer. The results from C-V characteristics indicated that the process with a modulated buffer layer would not induce extra charges trapping in the oxide bulk. II. NBTI and TDDB Characteristics FTIR spectra show that the Si-H and N-H density of the compressive SiN CESL is higher than those of ILD oxide, as shown in Fig. 6. Furthermore, the higher concentration of Si-H and N-H would induce serious degradation of NBTI, as shown in Fig. 7. Figure 8 illustrates the relationship between buffer layer thickness and NBTI characteristics for IO pMOSFETs. After stressing at Vg=-4.4V, 120C for 6000secs, serious ∆Vt shift of IO pMOSFETs could be observed without a buffer layer. As a very thin buffer layer-A was applied prior to the deposition of a highly compressive CESL, ∆Vt shift could be effectively suppressed. The buffer layer can be considered as a barrier to effectively screen the hydrogen diffusion from the compressive SiN CESL layer. Figure 9 shows the normalized lifetime as a function of Vg for core pMOSFETs with and without a buffer layer. Over two orders of magnitude of lifetime improvement could be achieved by the presence of the very thin buffer layer-A where there is no adverse impact on device performance enhancement. Moreover, much improvement of NBTI could be observed as the buffer layer thickness increased. The TDDB characteristics of IO pMOSFETs with a buffer layer were also improved, as shown in Fig. 10. Similar results have also been obtained by core pMOSFETs (not shown here). Furthermore, the charge pumping results from IO pMOSFETs are also shown in Fig. 11. Based on the results, a lower initial charge pumping current has been observed by the sample without a buffer layer and it indicates a low interface state. After stressing at Vg=-4.4V, 120C for 6000secs, however, the interface state without a buffer layer became seriously degraded. It is believed that weak Si-H bonds at interface state were formed from the compressive SiN CESL and the weak Si-H bonds could be easily broken by a highly electrical field stressing [7]. On the other hand, the modulated buffer layer could provide a barrier to screen hydrogen diffusion and further improve the reliability of pMOSFETs. Conclusions Instead of the complex SiGe refill scheme, 50% drive current enhancement of pMOSFETs with a compressive SiN CESL has been successfully applied for 45nm node CMOS and beyond. However, hydrogen incorporation from the compressive nitride CESL film must be substantially suppressed to solve the reliability degradation of NBTI and TDDB. In this study, a thin modulated buffer layer prior to the CESL deposition has been first demonstrated to improve the reliability of NBTI and TDDB without adverse impact on the drive current enhancement. Moreover, the NBTI lifetime for core pMOSFETs could be improved by over two orders of magnitude. References [1] K. Mistry, et al., pp. 50, VLSI, 2004. [2] R. Khamankar, et al., pp. 162, VLSI, 2004. [3] V. Chan, et al., pp. 3.8.1 IEDM, 2003. [4] F. Ootsuka et al., pp.575, IEDM, 2000. [5] T. Enda et al., pp.117, VLSI, 2001. [6] J.R. Shih, et al., pp.612, IRPS, 2003. [7] H.S. Rhee, et al., pp.709, IEDM, 2005. [8] M. Yamamura, et al., pp.88, VLSI, 2005. Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, Yokohama, 2006, -364F-6-1 pp. 364-365