Meng-Yi Wu

High-Speed InGaAs P-I-N Photodetector With Planar Buried Heterostructure

An InGaAs buried-heterostructure photodetector (BH-PD) was proposed and fabricated. By introducing etching and refilling with large bandgap and lower concentration semi-insulating InP, it was found that we can reduce the capacitance of P-I-N PDs by 33% without significantly increasing the reverse leakage current. It was also found that we can achieve a 3-dB bandwidth of 11.8 GHz from BH-PD, which was much larger than the 7.1-GHz 3-dB bandwidth observed from conventional InGaAs P-I-N PDs.

Highly scalable ballistic injection AND-type (BiAND) flash memory

An AND-type split-gate Flash memory cell with a trench select gate and a buried n/sup +/ source is proposed. This cell, programmed by ballistic source side injection (BSSI), can provide high programming efficiency with a cell size of 5F/sup 2/. Furthermore, both the programming speed and the read current are enhanced by the shared select gate configuration.

Comprehensively Study on a Ballistic-Injection AND-type Flash Memory Cell

In this paper, a novel ballistic-injection AND-type (BiAND) split gate flash memory, with a trench select gate and buried n+ source is proposed. The ballistic source side injection (BSSI) programming mechanism is performed and realized in a contactless AND array, which features high programming efficiency, 10-3–10-4 and small cell size of 5 F2. In addition, both the programming speed and read current is enhanced by the shared select gate structure. The BiAND flash memory is thus promising for low-voltage, high efficient, fast speed, scalable and high reliability non-volatile memory applications.

Investigation of temperature dependence on heterojunction bipolar light-emitting transistors embedded InGaAs/GaAs quantum wells

In this work, an analytical study of the temperature dependence of current gain and ideality factor (η) has been performed for the heterojunction bipolar light emitting transistor (HBLET). In order to utilize the radiative recombination, the structure of HBT embedded two quantum wells in the base region which can improve the radiation efficiency. Compare with the convention HBT, the temperature dependence of current gain increases 42.5% with increasing temperature from 350K followed by a decrease towards 300K. Variation of gain with temperature is different from that the characteristic of HBT adding another advantage in favor of the HBLET. The ηB of these devices are similar, revealing that the space-charge recombination dominates the overall base current. The high output power of HBLET is 962 μW at 88 mA. These results reveal that the HBLET which combine electrical and optical characteristic device.

Metal-oxide Thin Film Transistors with Co-sputtering Novel Aluminum Zinc Oxide Yttrium Channel Layer

Introduction Recently, metal oxide-based thin film transistors (TFTs) have attracted much attention because they have shown good electrical performance and can be manufactured at low temperatures to produce large-area displays with low cost. Metal oxide-based TFTs using Zn-O, In-Zn-O, In-Ge-Zn-O as an active channel have been widely studied. The important feature of these oxide channel materials is that they are multi-component and thus they have a large flexibility to tune the TFT-related properties. Due to the advantages of inexpensiveness, low electrical resistivity, high mobility and optical transparency in the visible region, aluminum zinc oxide (AZO) materials are investigated as transparent conductive oxide (TCO). But a few works of AZO material system are reported as a semiconductor layer for metal-oxide TFTs. In this report, we discuss the characteristics of novel aluminum zinc oxide yttrium (AZOY) channel-modulated component by r.f. co-sputtering for metal-oxide TFTs for this purpose.

Embedded ultra high density flash memory cell and corresponding array architecture

A novel flash memory cell fabricated by standard complementary metal oxide semiconductor (CMOS) logic process and its corresponding array architecture is presented. The cell which consists of two metal-oxide-semiconductor field effect transistors (MOSFET) in series is programmed by channel current induced drain avalanche hot hole and erased by channel hot electron injection. With novel operation principles and array architecture, a feature-sized n-MOSFET per non-volatile memory bit is successfully demonstrated and the CMOS-process-based flash cell size can be as small as multi-gated flash memory. The smallest bit area of a CMOS-process-based flash memory cell with good programming and erasing characteristics along with endurance up to 105 cycles, 10 years excellent read disturbance and data retention characteristics of data retention at 150°C is proposed. With its small cell size and full compatibility with standard CMOS logic process, the novel flash memory cell can be easily adapted in highly integrated very large scale integration (VLSI) systems.