Shyh-Fann Ting

Downscaling limit of equivalent oxide thickness in formation of ultrathin gate dielectric by thermal-enhanced remote plasma nitridation

The gate-oxide downscaling limit in thermal-enhanced remote plasma nitridation (RPN) process for forming ultrathin gate dielectric has been extensively investigated. In this work, the radical-induced re-oxidation effect has been observed as the base-oxide thickness less than 20 /spl Aring/. Nevertheless, for the base-oxide thickness thicker than 17 /spl Aring/, the RPN process still can effectively reduce the equivalent oxide thickness (EOT) and almost no transconductance degradation is observed. Further thinning of the base oxide will degrade the reduction of EOT and the transconductance with the RPN process, due to the penetration of nitrogen radicals into the active region. The physical and electrical properties of the ultrathin oxides (10 /spl sim/ 20 /spl Aring/) affected by this radical penetration have been studied extensively as well. Finally, the thinnest thickness has been estimated by compromising the feasible base-oxide thickness, the degradation of device performance, and the gate leakage criteria. Based on the forementioned criteria, we rind the 14 /spl Aring/ EOT to be the downscaling limit of the gate-oxide thickness.

The effect of remote plasma nitridation on the integrity of the ultrathin gate dielectric films in 0.13 μm CMOS technology and beyond

The authors report the effect of the remote plasma nitridation (RPN) process on characteristics of ultrathin gate dielectric CMOSFETs with the thickness in the range of 18 /spl Aring//spl sim/22 /spl Aring/. In addition, the effect of RPN temperature on the nitrogen-profile within the gate dielectric films has been investigated. Experimental results show that the thinner the gate dielectric films, the more significant effect on reducing the gate current and thinning the thickness of gate dielectric films by the RPN process. Furthermore, the minimum dielectric thickness to block the penetration of B and N has been estimated based on the experimental results. The minimum RPN gate dielectric thickness is about 12 /spl Aring/.

Determination of deep ultrathin equivalent oxide thickness (EOT) from measuring flat-band C-V curve

In this letter, a novel and simple method to determine deep ultrathin oxide thickness by measuring the MOS capacitance under the flat-band condition is reported. The mechanism of this method has been profoundly studied. The results determined by this method show good agreement with those using capacitance-voltage (C-V) simulation, ellipsometer, and high-resolution transmission electromicroscopy (HRTM) analysis for thin oxides (2/spl sim/3 nm). The thickness of pure oxide extracted by this method in this experiment can be down to 1.4 nm despite the obvious C-V distortion.

Thermally-enhanced remote plasma nitrided ultrathin (1.65 nm) gate oxide with excellent performances in reduction of leakage current and boron diffusion

Ultrathin thermally enhanced remote plasma nitrided oxides (TE-RPNO) with equivalent oxide thickness down to 1.65 nm are fabricated to investigate their leakage current reduction and boron diffusion barrier performances. A PMOSFET with TE-RPNO, compared to its conventional oxide counter-part, yields almost one order magnitude lower gate leakage current, less flatband voltage changes in high boron implantation dose or activation temperature, and shows broader process windows in the tradeoff between boron penetration and dopant activation.

A high breakdown-voltage SiCN/Si heterojunction diode for high-temperature applications

Cubic crystalline p-SiCN films are deposited on n-Si[100] substrates to form SiCN/Si heterojunction diodes (HJDs) with a rapid thermal chemical vapor deposition (RTCVD) technique. The developed SiCN/Si HJDs exhibit good rectifying properties up to 200/spl deg/C. At room temperature, the reverse breakdown voltage is more than 29 V at the leakage current density of 1.2/spl times/10/sup -4/ A/cm/sup 2/. Even at 200/spl deg/C, the typical breakdown voltage of SiCN/Si HJDs is still preserved about 5 V at the leakage current density of 1.47/spl times/10/sup -4/ A/cm/sup 2/. These properties are better than the /spl beta/-SiC on Si HJDs for high temperature applications.

High-quality ultrathin (1.6 nm) nitride/oxide stack gate dielectrics prepared by combining remote plasma nitridation and LPCVD technologies

Ultrathin nitride/oxide (N/O) gate dielectric stacks with equivalent oxide thickness of 1.6 nm have been fabricated by combining remote plasma nitridation (RPN) and low pressure chemical vapor deposition (LPCVD) technologies. NMOSFETs with these gate stacks exhibit good interface properties, improved subthreshold characteristics, low off-state currents, enhanced reliability, and about one order of magnitude reduction in gate leakage current to their oxide counterparts.

Dramatic improving luminous efficiency of organic light emitting diodes under low driving current using nitrogen doped hole transporter

Abstract In this letter, output luminance, current efficiency and power efficiency of the organic light emitting diodes (OLEDs) with N 2 doped hole transport layer (HTL) have been studied in detail. Experimental results show that the current efficiency and the power efficiency thus in turn the output luminance of OLEDs prepared with HTL evaporated in the optimum N 2 gas ambient pressure of 1×10 −4 Torr are improved about 13, 9 and 12 times, respectively, under 2.7 mA/cm 2 driving current. The significant improving mechanism has been illustrated comprehensively with a series of schematic models.

Improving turn on voltage and driving voltage of organic electroluminescent devices with nitrogen doped electron transporter

Abstract In this letter, I/V curves, output luminance of the organic light emitting diodes (OLEDs) with N2 doped electron transport layer (ETL) have been studied in detail. Experimental results show that the turn on voltage and driving voltage of OLEDs with ETL evaporated in the optimum N2 gas ambient pressure of 1×10−4 Torr are reduced from 3.5 to 1 V and 7.7 to 5.7 V, respectively. The significant improving mechanism has been illustrated comprehensively with a schematic energy diagram model.

Cubic Single-Crystalline Si1 − x − y C x N y Films with Mirror Face Prepared by RTCVD

© The Electrochemical Society, Inc. [2001]. All rights reserved. Except as provided under U.S. copyright law, this work may not be reproduced, resold, distributed, or modified without the express permission of The Electrochemical Society (ECS). The archival version of this work was published in [Electrochemical and Solid-State Letters, Vol.4, No.11, pp.G91-G93].”

Development of a new contact-type piezoresistive micro-shear-stress sensor

A prototype contact type micro piezoresistive shear-stress sensor that can be utilized to measure the shear stress between skin of stump and socket of Above-Knee (AK) prosthesis was designed, fabricated and tested. Micro-electro-mechanical system (MEMS) technology has been chosen for the design because of the low cost, small size and adaptability to this application. In this paper, the Finite Element Method (FEM) package ANSYS has been employed for the stress analysis of the micro shear-stress sensors. The sensors contain two X-ducers that will transform the stresses into an output voltage. In the developed sensor, a 3000X3000X3000 micrometers (superscript 3/ square membrane is formed by bulk micromachining of an n-type <100> monolithic silicon. The piezoresistive strain gauges were implanted with boron ions with a dose of 10(superscript 15/ atoms/cm(superscript 2/. Static characteristics of the shear sensor were determined through a series of calibration tests. The fabricated sensor exhibits a sensitivity of 0.13mV/mA-Mpa for a 1.4N full scales shear force range and the overall mean hysteresis error is than 3.5%. In addition, the results simulated by FEM are validated by comparison with experimental investigations.