Li Yan Siow

Double side redistribution layer process on embedded wafer level package for package on package (PoP) applications

In this paper, an embedded wafer level package with Cu through mold via (TMV) interconnects was developed for package on package (PoP) application. Cu pillar interconnects for different heights were fabricated on daisy chain test chips and sacrificial chips. The daisy chain test chips were then stacked onto the sacrificial chips using die attach film, and the chip stacks were picked and placed onto a molding tape for mold encapsulation to form a re-configured wafer. The reconfigured wafer was mechanically backgrinded on both sides to remove sacrificial chips and to expose the Cu TMV. The thinned re-configured wafer was temporarily bonded to a stiff Si carrier using a temporary adhesive, in order to reduce the wafer warpage to enable wafer level processing of the Cu redistribution layers (RDL). After front side RDL processing, the re-configured wafer is de-bonded and re-bonded for backside RDL processing. The warpage value of the reconfigured wafer was measured during different process steps and through-scan was performed using a scanning acoustic microscope to inspect the quality of temporary bonding of re-configured wafers to a Si carrier. Electrical test shows good connectivity between front and back side RDL with Cu TMV, thus enabling embedding wafer level package for PoP application.

Evaluation of support wafer system for thin wafer handling

The optimization of the temporary wafer bonding process for thin wafers handling is reported. Two temporary bonding materials are evaluated with two low temperature cure (200degC) dielectrics. TGA results show that the dielectric materials are more stable at high temperature (260degC) with not more than 1% weight loss while the temporary bonding adhesives gave a higher weigh loss of 5.5%. It is found that optimal dehydration bake on both device and carrier wafer can create a void-free bonding. The dielectric and bonding material compatibility is also important to prevent temporary bonding from voiding.

A Miniaturization Strategy for Harvesting Vibration Energy Utilizing Helmholtz Resonance and Vortex Shedding Effect

In this letter, we report a miniaturization strategy for harvesting a low-frequency random vibration energy with a piezoelectric energy harvesting (EH) system utilizing coupled Helmholtz resonance and vortex shedding effect. This is made possible by transferring the low-frequency vibration energy into a pressurized fluid, which is in turn converted into predefined, pressure-independent high-frequency energy harvested by the device. The vibration-pressurized fluid conversion extends the device sampling frequency band; enables efficient harvesting of broadband low vibration frequencies with small form factor. Proof of concept of the proposed strategy has been demonstrated with an AlN-based MEMS EH, which delivered an output power density of 95.5 mW/cm3 under a constant input airflow at 4.2 lbf/in2 pressure.

Fine pitch solder-less bonding using ultrasonic technique

Industry is adapting micro-bumps in the device structures in order to having module with multiple functions and capabilities within smaller area. Micro-bumps is coated with Tin (Sn) cap to facilitates solder interconnects formation between the chip and substrate. Electrochemical migration failure is a known issue related to flux residue on the solder joints after the thermal compression of the chip with solder cap micro-bumps on substrate. Electromigration is another issue related to shrinking interconnects. It is related to atomic displacement in a conductor line due to an applied current. In this study, the micro bumps are directly bonded to the substrate without solder cap and thus there is no electro migration failure concern. The chip used in this study is of size 7mm × 7mm × 0.05mm and consists of peripheral micro-solder bumps at 40μm pitch with no solder cap. Ultra-sonic process was adopted to form the direct metal to metal joint between the chip and substrate. Ultrasonic process offered several advantages such as lower bonding temperature and shorter bonding duration over thermal compression process. However, the US process demand bumps with good co-planity of less than 0.6μm and good surface finishing. The copper bumps were coated either with TiAu, ENEPIG, and ENEP to prevent oxidation occurring during the bonding process. Detail DOE experiment was conducted to evaluate the bonding quality. Shear test and x-section analysis revealed that chips coated with either TiAu or ENEPIG could form a bond on silicon substrate coated with TiAu with optimized US parameters. The developed US bonding process successfully demonstrated on C2C application.

Evaluation of ultra thick photo resist for high aspect ratio bumping applications

This paper presents the evaluation results of two positive, thick resist molds for the electroplating of Copper pillar interconnects. Two different resist molds of 100um and 58um thickness have been fabricated with aspect ratios of 2.5 and 1.3 respectively in a single coat process. Lithography parameters have been optimized using a UV aligner to produce smooth and near vertical sidewall profiles for both resist molds. Through mold electroplating of Copper has also been demonstrated with good uniformity within ± 3% and ±2% respectively. The resist molds were also found to be stripped easily in standard solvent strippers making them suitable for fabrication of high aspect ratio interconnects.

Challenges and approaches of ultra-fine pitch Cu pillar assembly on organic substrate using wafer level underfill

The use of flip-chip technology in packaging interconnects is becoming more important due to its better electrical performance, smaller form factor packages, and higher interconnect density than wire bonded packages. Flip-chip soldering has been the mainstream flip-chip technology. However, the move towards fine pitch Cu pillar flip chip packaging with fine pad bond pitch has driven the investigation of Sn plated bumps on Cu pillar encapsulated with wafer level underfill as a potential alternative [1]. As the pitch of the electrical interconnections decreases and chip size increases, it is more difficult to develop high through-put processes using conventional capillary flow underfills. A WLUF process eliminates the time required to dispense conventional underfill to every chip and for capillary flow [2]. Fillers are used in underfill materials to decrease the coefficient of thermal expansion (CTE) which has the effect of reducing package stresses, and helping to achieve better reliability performance. However, in the case of WLUF with high filler content, it is very challenging to achieve 100% electrically and metallurgically good Pb-free solder joints and void-free underfill as the epoxy based WLUF can cure early, below the Pb-free solder melting temperature, and become trapped between flip chip bumps and substrate solder pads. Also, the high process temperature of Pb-free solder can cause a large amount of voids to form within the WLUF material during the solder joining cycle [3-4]. In the paper, a WLNCF with 40% fillers was laminated onto 8 inch wafer containing Cu pillar post with Sn solder bumps by spin coating. The wafer was diced into chips. A chip was aligned and joined to a substrate with an optimized heating and cooling cycle. The effects of the bonding parameters and bonding temperature profile on the fine pitch flip chip assembly on solder wetting, solder joint shape and WLNCF voids are addressed in this paper. The main challenge for the fine pitch flip chip assembly was to assemble a fine pitch Cu pillar assembly onto an organic substrate while ensuring good solder wetting, good bonding placement accuracy, minimum solder joint voids, good fillet coverage and no wafer level underfill trapped between the solder and substrate bond pad after thermocompression bonding. In addition, wafer level underfill lamination uniformity and voids after lamination and B-stage cure were inspected. Wafer dicing evaluation was also performed to ensure no debris or particles adhering to the WL-NCF during dicing. No peeling or delamination of the WL-NCF was observed after dicing. The impact of these various factors on the stacked die assembly is discussed in this paper.

Fine pitch Cu pillar wafer process development and seed layer etching characterization

This paper will revise the traditional wafer fabrication process flow to accommodate the new material used to achieve 40 um fine pitch Cu pillar with minimize seed layer undercut. New photo-resist material is introduced to attain a single coating of 40um thickness and it has demonstrated the capability of attaining an aspect ratio of 2. The wafer fabrication process ended using a combination of seed layer (Ti/Cu) wet and dry etching. It has shown the potential of achieving almost zero undercut which is very critical for a 20um via. Cross-sectional SEM will be carried out to verify the side wall profile and the footing of the photo-resist. FIB cross-section is done to identify Ti and Cu undercut. Bump shear test will be performed after the seed layer etching to quantify the failure mode of a bump with and without seed layer undercuts.

Wafer-Level Vacuum-Packaged Piezoelectric Energy Harvesters Utilizing Two-Step Three-Wafer Bonding

This paper reports on the successful implementation of a wafer-level vacuum-packaged, CMOS-compatible aluminum nitride (AlN) based microelectromechanical system (MEMS) energy harvester (EH). The reported EH features high Q-factor (709.3) and high-g survivability (harmonic at 20g), achieved through wafer-level vacuum-package scheme which reduces the air damping effect and increases the Q-factor, overcoming the tradeoff between vibration amplitude and output power density for EHs operated in air. A power of 468.77µW, bandwidth of 71Hz (3.66%) is delivered by a ~0.119cm3 footprint (1×0.7×0.1705cm3) EH at 20g sinusoidal input vibration, equates to a record power density of ~3.93mW/cm3. This novel packaging and design scheme, which utilizes two-step three-wafer wafer level eutectic bonding, allows size reduction and shock-resilience improvement of future EH. The ability to harvest broad spectrum mechanical vibration energy with small footprint and high-g survivability, makes the reported EH one step closer towards powering the next generation battery-less Smart Tire Pressure Monitoring System (TPMS). Furthermore, the whole integration process, including the wafer-level vacuum-packaging process, is CMOS compatible, making the reported EH viable for mass production with low fabrication cost.

A high efficiency frequency pre-defined flow-driven energy harvester dominated by on-chip modified Helmholtz Resonating cavity

We present a novel flow-driven energy harvester with its frequency dominated by on-chip modified Helmholtz Resonating Cavity (HRC). This device harvests pneumatic kinetic energy efficiently and demonstrates a power density of 117.6 μW/cm2, and charging of a 1 μF capacitor in 200 ms.

Correction to “A Miniaturization Strategy for Harvesting Vibration Energy Utilizing Helmholtz Resonance and Vortex Shedding Effect” [Feb 14 271-273]

In the above paper , there are two typos in the abstract and last page. The 95.5