Tai Chong Chai

Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps

Most TSVs are filled with copper; siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5 times 10-6/degC) is a few times higher than that of silicon (~2.5 times10-6/degC). Thus, when the copper filled through silicon via (TSV) is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO2), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this paper, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moores (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as 10 times 10-6/degC. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for 1) making a decision if underfill is necessary for the reliability of microbumps and 2) selecting underfill materials to minimize the stresses and strains in the microbumps.

Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps

Most of TSVs are filled with the copper, even siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5x10-6/degC) is a few times higher than that of silicon (~2.5x10-6/degC). Thus, when the copper filled TSV is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO2), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this study, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moores (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as 10x10-6/degC. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for (1) making a decision if underfills are necessary for the reliability of microbumps, and (2) selecting underfill materials to minimize the stresses and strains in the microbumps.

Electromigration performance of Through Silicon Via (TSV) – A modeling approach

The electromigration (EM) performance of Through Silicon Via (TSV) in silicon interposer application are studied using Finite Element (FE) modeling. It is found that thermo-mechanical stress is the dominant contribution factor to EM performance in TSV instead of the current density. The predicted failure site is dependent on the process technology, and exhibits asymmetric behavior if different process is used between the top and bottom metallization of a TSV. Modeling is also done for two different coverage patterns of top metallization, namely (i) the metal line covers the via completely, and (ii) the metal line only extends to the centre of the via, covering half of the via. The simulation results of the latter model show the existence of a second EM failure site and worse EM performance is expected. This additional possible EM failure site is further confirmed through dynamic simulation of void growth.

Electromigration study of 50 µm pitch micro solder bumps using four-point Kelvin structure

Electromigration (EM) of micro bumps of 50 µm pitch was studied using four-point Kelvin structure. Two kinds of bumps, i. e., SnAg solder bump and Cu post with SnAg solder were tested. These bumps with thick Cu under bump metallization (UBM) were bonded with electroless Ni/Au (ENIG) pads. The results showed different EM features comparing with larger flip chip joints. Under various test temperatures from 100 to 140 °C, the increasing of electrical resistance under current stressing was mainly due to the formation of the high temperature intermetallic compounds (IMCs). The resistance increase-rate in solder bump interconnects was faster than that of Cu post with SnAg bump joints since there was more low temperature solder and under current stressing, more IMCs would be formed. When Cu post with SnAg bumps were tested at 140 °C with the current density of 4.08×104 A/cm2, after certain stressing time the resistances would reach a plateau region, where the diffusion between different materials, i. e., Cu, Ni and Sn reached equilibrium, and IMCs became stable. Large number of Kirkendall voids and a number of cracks were found in the Cu post interconnects which was caused by the electron wind since less voids and cracks were found in the adjacent bump interconnects. When Cu post with SnAg bumps were tested at 140 °C with the current density of 2.04×104 A/cm2 for 1000 h, the resistance did not reach steady state. The electron flow direction also has an effect on the diffusion of materials. The degradation of resistance increased faster when electrons flow from Cu UBM to ENIG.

Thermo-mechanical finite element analysis in a multichip build up substrate based package design

Abstract This paper presents a thermo-mechanical analysis of a multichip module (MCM) package design, with emphasis on the package warpage, thermally induced stress and the second level solder joint reliability. The MCM package contains four flip chips which are mounted on a build up substrate. First, the effect of the positioning of four silicon dice within the MCM package on the warpage of the package is studied. Second, the effect of package dimensions (the heat spreader thickness, the structural adhesive thickness and the substrate thickness) on the maximum residual stress as well as the warpage of the package is performed. Finally, this paper presents a 3D sliced model for solder joint reliability of the MCM assembly. A creep constitutive relation is adopted for the 63Sn/37Pb solder to account for its time and temperature dependence in thermal cycling. The fatigue life of solder joint is estimated by the Darveauxs approach. A series of parametric study is performed by changing the package dimensions. The results show that the largest die tends to experience highest stresses at its corner and has more influence on the warpage of the package than smaller dice. The results also show the most sensitivity factors that affect the package warpage and the second level solder joint reliability are the substrate thickness and the heat spreader thickness. The structural adhesive thickness has no major effect on the package warpage, the maximum von Mises stress of the package and the second level solder joint reliability.

Si -based microphone testing methodology and noise reduction

In this paper two different packaging and testing approaches were studied for Si based microphone. Microphone performance was tested with Ceramic, Plastic and metal packages. Sensitivity testing of microphone is done when it is connected to an ASIC die. Testing was done with microphone and ASIC packaged separately and also in a single package. Substantial noise was generated when microphone and ASIC are tested separately in a PCB. Noise was detected after 150 Hz with the noise intensity reducing as it goes to higher frequencies. This was observed regardless of the packaging schemes. Different shielding methods were tried and found that copper foil shielding results in substantial noise reduction during frequency response testing and a flat response curve was observed with metal can package. Form this new testing methodology, it is demonstrated that same ASIC can be used repeatedly during microphone testing and hence some cost reduction can be expected.

Reliability of a Silicon Stacked Module for 3-D SiP Microsystem

Solder joint reliability of 3-D silicon carrier module were investigated with temperature cycle and drop impact test. Mechanical simulation was carried out to investigate the solder joint stress using finite element method (FEM), whose 3-D model was generated and solder fatigue model was used. According to the simulation results, the stress involved between flip chip and Si substrate was negligible but stress is more concentrated between Si carriers to printed circuit board (PCB) solder joint area. Test vehicles were fabricated using silicon fabrication processes such as DRIE, Cu via plating, SiO deposition, metal deposition, lithography, and dry or wet etching. After flip chip die and silicon substrate fabrication, they were assembled by flip chip bonding equipment and 3-D silicon stacked modules with three silicon substrate and flip chip dies were fabricated. Daisy chains were formed between flip chip dies and silicon substrate and resistance measurement was carried out with temperature cycle test (C, 2 cycles/h). The tested flip chip test vehicles passed T/C 5000 cycles and showed robust solder joint reliability without any underfill material. Drop test was also carried out by JEDEC standard method. More details on test vehicle fabrication and reliability test results would be presented in the paper.

Reliability studies of a through via silicon stacked module for 3D microsystem packaging

In this study, two types of reliability tests are studied for silicon stacked module. One is for temperature cycle solder joint reliability. Another is for drop impact test. Test vehicles are fabricated using silicon fabrication processes such as SiO2 deposition, metal deposition, lithography, through via formation, copper plating and dry or wet etching. After flipchip die and silicon substrate fabrication, they are assembled by flipchip bonder. Daisy chains are formed between flipchip dies and each silicon substrates and resistance measurement is carried out with temperature cycle test (-40/125degC, 2cycles/hr). In case of drop test, the JESD recommended condition B (e.g. 1500 G, 0.5 millisecond duration, and half-sine pulse) is adopted. And in-situ monitoring is carried out to observe the failure during the drop test. Reliability results of through via silicon stacked module indicated that it passed 1000 cycles T/C and survived drop impact test

Development of Large Die Fine-Pitch Cu/Low-

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-μm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.

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A ball bonding process in wire bonding generally involves impact followed by ultrasonic (US) bonding prior to wedge bonding. During the ball bonding process, the impact force flattening the free-air ball introduces significant localized out-of-plane compressive stress on the pad and the low-k structure beneath. The subsequent process of US bonding induces in-plane and shear stresses to the structure. High induced stress during bonding is not desirable, as it may lead to pad damage or cratering of the silicon structure. In this paper, we report on studies conducted on using four piezoresistive sensors embedded underneath the center of the bond pad for the evaluation of in-plane and out-of-plane stresses, which covers both the impact and US stages during the ball bonding process. Different levels of impact force, bond force, bonding duration, and US power are investigated using gold wire bonding for feasibility and sensitivity studies of the stress sensors. Fast Fourier transform (FFT) and inverse FFT are used for noise filtering and to isolate the US signal yielding a continuous output signal from the in situ measurement of contact and US stages during the ball bonding process. It is found that the stress sensors are sensible to capture different impact force, bond force, bonding duration, and US power.