Li Zhiqun

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18 m CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range. Furthermore, a method of adding a precharging current source is proposed to increase the initial charge current, which will speed up the settling time of CPPLLs. Test results show that the current mismatching can be less than 0.4% in the output voltage range of 0.4 to 1.7 V, with a charge pump current of 100 A and a precharging current of 70 A. The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.

A CMOS image-rejection mixer with 58-dB IRR for DTV receivers

The design, implementation, and characterization of an image-rejection double quadrature conversion mixer based on RC asymmetric polyphase filters (PPF) are presented. The mixer consists of three sets of PPFs and a mixer core for quadrature down conversion. Two sets of PPFs are used for the quadrature generation and the other one is used for the IF signal selection to reject the unwanted image band. Realized in 0.18-μm CMOS technology as a part of the DVB-T receiver chip, the mixer exhibits a high image rejection ratio (IRR) of 58 dB, a power consumption of 11 mW, and a 1-dB gain compression point of −15 dBm.

A CMOS Gm−C complex filter with on-chip automatic tuning for wireless sensor network application

A Gm?C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 ?m CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage.

Design and optimization of CMOS LNA with ESD protection for 2.4 GHz WSN application

A new optimization method of a source inductive degenerated low noise amplifier (LNA) with electrostatic discharge protection is proposed. It can achieve power-constrained simultaneous noise and input matching. An analysis of the input impedance and the noise parameters is also given. Based on the developed method, a 2.4 GHz LNA for wireless sensor network application is designed and optimized using 0.18-μm RF CMOS technology. The measured results show that the LNA achieves a noise figure of 1.59 dB, a power gain of 14.12 dB, an input 1 dB compression point of −8 dBm and an input third-order intercept point of 1 dBm. The DC current is 4 mA under a supply of 1.8 V.

A 30-dB 1–16-GHz low noise IF amplifier in 90-nm CMOS

This paper presents a high-gain wideband low-noise IF amplifier aimed for the ALMA front end sys- tem using 90-nm LP CMOS technology. A topology of three optimized cascading stages is proposed to achieve a flat and wideband gain. Incorporating an input inductor and a gate-inductive gain-peaking inductor, the active shunt feedback technique is employed to extend the matching bandwidth and optimize the noise figure. The circuit achieves a flat gain of 30.5 dB with 3 dB bandwidth of 1-16 GHz and a minimum noise figure of 3.76 dB. Under 1.2 V supply voltage, the proposed IF amplifier consumes 42 mW DC power. The chip die including pads takes up 0.53 mm 2 , while the active area is only 0.022 mm 2 .

A 2.4GHz low-IF RF frontend for wireless sensor networks

This paper presents a low-power low-IF RF frontend for 2.4GHz wireless sensor networks (WSN) in 0.18μm RF CMOS technology. The RF frontend consists of a variable gain low noise amplifier (VG-LNA), a quadrature passive mixer and a divide-by-two circuit which generates the differential quadrature LO signals for quadrature balanced mixer. The effect of the input parasitic capacitance on the inductively degenerated common source LNAs input impedance is analyzed in detail. An external LC network was used to achieve input matching under low power consumption. The proposed VG-LNA has three gain modes: high gain, medium gain and low gain modes. The gain control function can accommodate a high input level and satisfy the need dynamic range of WSN. The passive mixer shows high linearity, low 1/f noise and near zero power consumption. The measurement results of the frontend achieve 15dB voltage conversion gain, 4dB noise figure at the high gain mode, −1.5dBm input third order intercept point at the low gain mode, while the DC power consumption is 10.4 mW under a 1.8V supply voltage.

A wideband variable gain differential CMOS LNA for multi-standard wireless LAN

This paper describes a wideband variable gain LNA for multi-standard wireless LAN operating in the frequency bands of 4.9-5.825 GHz, including three standards: IEEE 802.11a, ETSI HiperLAN2 and MMAC HiSWANa. By using a simple feedback loop at the second stage of LNA we realized the continuous gain control. A variable gain range of 18.7 dB (0.7 dB to 19.4 dB) is achieved. The noise figure is 1.1 dB at the maximum gain and the input 1-dB compression point is -3.5 dBm at the minimum gain, while the DC power consumption is 12.6 mW under a 1.8 V supply voltage.

A 60 GHz down-conversion mixer using a novel topology in 65 nm CMOS

A 60 GHz down-conversion mixer used in the unlicensed 60 GHz band system in 65-nm CMOS technology is presented in this paper. Based on the double-balanced Gilbert cell, the mixer comprises a cross-coupled pair to rise conversion gain and two series LCR network resonating at IF frequency to enhance bandwidth. As a result, both high gain and broad bandwidth are achieved. From the simulation results, the conversion gain exceeds 10 dB and 3-dB IF bandwidth is from 8 GHz to 16 GHz, the OP1dB is -6 dBm and noise figure is below 12 dB in band of interest. The mixer consumes 5 mA from a 1.2 V supply without buffer, and the chip area is 1×0.75 mm2 with pads.

Design of low power common-gate low noise amplifier for 2.4 GHz wireless sensor network applications

This paper presents a differential low power low noise amplifier designed for the wireless sensor network (WSN) in a TSMC 0.18 μm RF CMOS process. A two-stage cross-coupling cascaded common-gate (CG) topology has been designed as the amplifier. The first stage is a capacitive cross-coupling topology. It can reduce the power and noise simultaneously. The second stage is a positive feedback cross-coupling topology, used to set up a negative resistance to enhance the equivalent Q factor of the inductor at the load to improve the gain of the LNA. A differential inductor has been designed as the load to achieve reasonable gain. This inductor has been simulated by the means of momentum electromagnetic simulation in ADS. A “double-π circuit model has been built as the inductor model by iteration in ADS. The inductor has been fabricated separately to verify the model. The LNA has been fabricated and measured. The LNA works well centered at 2.44 GHz. The measured gain S21 is variable with high gain at 16.8 dB and low gain at 1 dB. The NF (noise figure) at high gain mode is 3.6 dB, the input referenced 1 dB compression point (IP1dB) is about −8 dBm and the IIP3 is 2 dBm at low gain mode. The LNA consumes about 1.2 mA current from 1.8 V power supply.

An I/Q mixer with an integrated differential quadrature all-pass filter for on-chip quadrature LO signal generation

A down-conversion in-phase/quadrature (I/Q) mixer employing a folded-type topology, integrated with a passive differential quadrature all-pass filter (D-QAF), in order to realize the final down-conversion stage of a 60 GHz receiver architecture is presented in this work. Instead of employing conventional quadrature generation techniques such as a polyphase filter or a frequency divider for the local oscillator (LO) of the mixer, a passive D-QAF structure is employed. Fabricated in a 65 nm CMOS process, the mixer exhibits a voltage gain of 7-8 dB in an intermediate frequency (IF) band ranging from 10 MHz-1.75 GHz. A fixed LO frequency of 12 GHz is used to down-convert a radio frequency (RF) band of 10.25-13.75 GHz. The mixer displays a third order input referred intercept point (IIP 3 ) ranging from -8.75 to -7.37 dBm for a fixed IF frequency of 10 MHz and a minimum single-sideband noise figure (SSB-NF) of 11.3 dB. The mixer draws a current of 6 mA from a 1.2 V supply voltage dissipating a power of 7.2 mW.