Lieuwe B. Leene

A compact recording array for neural interfaces

This paper presents a 44-channel front-end neural interface for recording both Extracellular Action Potentials (EAPs) and Local Field Potentials (LFPs) with 60 dB dynamic range. With a silicon footprint of only 0.015 mm2 per recording channel this allows an unprecedented order of magnitude area reduction over state-of-the-art implementations in 0.18 μm CMOS. This highly compact configuration is achievable by introducing an in-channel Sigma Delta assisted Successive Approximation Register (ΣΔ-SAR) hybrid data converter integrated into the analogue front-end. A pipelined low complexity FIR filter is distributed across 44-channels to resolve a 10-bit PCM output. The proposed system achieves an input referred noise of 6.41 μVrms with a 6 kHz bandwidth and sampled at 12.5 kS/s, with a power consumption of 2.6 μW per channel.

Continuous-time micropower interface for neural recording applications

This paper presents a novel amplifier architecture intended for low power neural recording applications. By using continuous-time signal representation, the proposed topology predominantly leverages digital topologies taking advantage of efficient techniques used in time domain systems. This includes higher order feedback dynamics that allow direct analogue signal quantization and near ideal integrator structures for noise shaping. The system implemented in 0.18 μm standard CMOS demonstrates the capability for low noise instrumentation with a bandwidth of 6 kHz and highly linear full dynamic range. Simulation results indicate 1.145 μW budget from 0.5 V supply voltage with an input referred thermal noise of 7.7 μVrms.

A 0.45V continuous time-domain filter using asynchronous oscillator structures

This paper presents a novel oscillator based filter structure for processing time-domain signals with linear dynamics that extensively uses digital logic by construction. Such a mixed signal topology is a key component for allowing efficient processing of asynchronous time encoded signals that does not necessitate external clocking. A miniaturized primitive is introduced as analogue time-domain memory that can be modelled, synthesized, and incorporated in closed loop mixed signal accelerators to realize more complex linear or non-linear computational systems. This is contextualized by demonstrating a compact low power filter operating at 0.45 V in 65 nm CMOS. Simulation results are presented showing an excess of 50 dB dynamic range with a FOM of 7fJ/pole which promises an order of magnitude improvement on state-of-the-art filters in nanometre CMOS.

A 0.5V time-domain instrumentation circuit with clocked and unclocked ΔΣ operation

This paper presents a time-domain instrumentation circuit with exceptional noise efficiency directed at using nano metre CMOS for next generation neural interfaces. Current efforts to realize closed loop neuromodulation and high fidelity BMI prosthetics rely extensively on digital processing which is not well integrated with conventional analogue instrumentation. The proposed time-domain topology employs a differential ring oscillator that is put into feedback using a chopper stabilized low noise transconductor and capacitive feedback. This realization promises better digital integration by extensively using time encoded digital signals and seamlessly allows both clocked & unclocked ΔΣ behavior which is useful on-chip characterization and interfacing with synchronous systems. A 0.5 V instrumentation system is implemented using a 65 nm TSMC technology to realize a highly compact footprint that is 0.006 mm2 in size. Simulation results demonstrate an excess of 55 dB dynamic range with 3.5 μVrms input referred noise for the given 810 nW total system power budget corresponding to an NEF of 1.64.

Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures

The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-voltage operation. First- and second-order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modeled precisely to realize more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65-nm CMOS technology to realize a fourth-order low-pass Butterworth filter. The system utilizes a 0.5-V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73-nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio of 53 dB with a narrow 5-kHz bandwidth resulting in an figure-of-merit of 8.2 fJ/pole. With this circuit occupying a compact 0.004-mm2 silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters, whilst additionally offering direct integration with digital systems.

A 2.7μW/MIPS, 0.88GOPS/mm 2 distributed processor for implantable brain machine interfaces

This paper presents a scalable architecture in 0.18 μm CMOS for implantable brain machine interfaces (BMI) that enables micro controller flexibility for data analysis at the sensor interface. By introducing more generic computational capabilities the system is capable of high level adaptive function to potentially improve the long term efficacy of invasive implants. This topology features a compact ultra low power distributed processor that supports 64-channel neural recording system on chip (SOC) with a computational efficiency of 2.7 μW/MIPS with a total chip area of 6.2 mm2. This configuration executes 1024 instructions on each core at 20 MHz to consolidate full spectrum high precision recordings from 4 analogue channels for filtering, spike detection, and feature extraction in the digital domain.

A novel neural recording system utilising continuous time energy based compression

This work presents a new data compression method that uses an energy operator to exploit the correlated energy in neural recording features in order to achieve adaptive sampling. This approach enhances conventional data converter topologies with the power saving of asynchronous systems while maintaining low complexity & high efficiency. The proposed scheme enables the transmission of 0.7kS/s, while preserving the features of the signal with an accuracy of 95%. It is also shown that the operation of the system is not susceptible to noise, even for signals with 1dB SNR. The whole system consumes 3.94μW with an estimated area of 0.093mm2.

A 890fJ/bit UWB transmitter for SOC integration in high bit-rate transcutaneous bio-implants

The paper presents a novel ultra low power UWB transmitter system for near field communication in transcutaneous biotelemetries. The system utilizes an all-digital architecture based on minising the energy dissipated per bit transmitted by efficiently encoding a packet of pulses with multiple bits and utilizing oscillator referenced delays. This is achieved by introducing a novel bi-phasic 1.65pJ per pulse UWB pulse generator together with a 72 μW DCO that provide a transmission bandwidth of 77.5 Mb/s with an energy efficiency of 890 fJ per bit from a 1.2 V supply. The circuit core occupies a compact silicon footprint of 0.026 mm2 in a 0.18μm CMOS technology.