Song Luan

Neuromodulation: present and emerging methods.

Neuromodulation has wide ranging potential applications in replacing impaired neural function (prosthetics), as a novel form of medical treatment (therapy), and as a tool for investigating neurons and neural function (research). Voltage and current controlled electrical neural stimulation (ENS) are methods that have already been widely applied in both neuroscience and clinical practice for neuroprosthetics. However, there are numerous alternative methods of stimulating or inhibiting neurons. This paper reviews the state-of-the-art in ENS as well as alternative neuromodulation techniques—presenting the operational concepts, technical implementation and limitations—in order to inform system design choices.

A novel charge-metering method for voltage mode neural stimulation

Electrical neural stimulation is the technique used to modulate neural activity by inducing an instantaneous charge imbalance. This is typically achieved by injecting a constant current and controlling the stimulation time. However, constant voltage stimulation is found to be more energy-efficient although it is challenging to control the amount of charge delivered. This paper presents a novel, fully integrated circuit for facilitating charge-metering in constant voltage stimulation. It utilises two complementary stimulation paths. Each path includes a small capacitor, a comparator and a counter. They form a mixed-signal integrator that integrates the stimulation current onto the capacitor while monitoring its voltage against a threshold using the comparator. The pulses from the comparator are used to increment the counter and reset the capacitor. Therefore, by knowing the value of the capacitor, threshold voltage and output of the counter, the quantity of charge delivered can be calculated. The system has been fabricated in 0.18 μm CMOS technology, occupying a total active area of 339 μm × 110 μm. Experimental results were taken using: (1) a resistor-capacitor EEI model and (2) platinum electrodes with ringer solution. The viability of this method in recruiting action potentials has been demonstrated using a cuff electrode with Xenopus sciatic nerve. For a 10 nC target charge delivery, the results of (2) show a charge delivery error of 3.4% and a typical residual charge of 77.19pC without passive charge recycling. The total power consumption is 45 μW. The performance is comparable with other publications. Therefore, the proposed stimulation method can be used as a new approach for neural stimulation.

Live demonstration: A scalable 32-channel neural recording and real-time FPGA based spike sorting system

This demo presents a scalable a 32-channel neural recording platform with real-time, on-node spike sorting capability. The hardware consists of: an Intan RHD2132 neural amplifier; a low power Igloo® nano FPGA; and an FX3 USB 3.0 controller. Graphical User Interfaces for controlling the system, displaying real-time data, and template generation with a modified form of WaveClus are demonstrated.

Towards an inductively coupled power/data link for bondpad-less silicon chips

This paper explores the concept of developing a bondpad-less fully-integrated inductive link for power/data transfer between a CMOS Integrated Circuit (IC) and a PCB. A key feature of the implemented system is that it requires no off-chip components. The proposed chip uses a standard 0.35 µm process and occupies an area of 2.5mm×2.5mm and an on-chip inductor occupies an area of 1.5mm×1.5mm. At 900MHz, 9mW was designed to be provided to the chip (up to 22.5mW with a total efficiency of 5%). Binary Phase Shift Keying (BPSK) and Load shift keying (LSK) are used for the the PCB-to-chip and chip-to-PCB link respectively for half-duplex communication. An Injection-Locked-Oscillator-based BPSK demodulator is implemented on-chip to save power. The maximum data rate for the PCB-to-chip link is 10Mb/s. The estimated area of the circuitry is only 2mm2 which is 32% of the total chip area.

An event-driven SoC for neural recording

This paper presents a novel 64-channel ultra-low power/low noise neural recording System-on-Chip (SoC) featuring a highly reconfigurable Analogue Front-End (AFE) and block-selectable data-driven output. This allows a tunable bandwidth/sampling rate for extracting Local Field Potentials (LFPs) and/or Extracellular Action Potentials (EAPs). Realtime spike detection utilises a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The 64-channels are organised into 16 sets of 4-channel recording blocks, with each block having a dedicated 10-bit SAR ADC that is time division multiplexed among the 4 channels. Each channel can be individually powered down and configured for bandwidth, gain and detection threshold. The output can thus combine continuous-streaming and event-driven data packets with the system configured as SPI slave. The SoC is implemented in a commercially-available 0.35 μm CMOS technology occupying a silicon area of 19.1 mm2 (0.3 mm2 gross per channel) and requiring 32 μW/channel power consumption (AFE only).

A 32-ch. bidirectional neural/EMG interface with on-chip spike detection for sensorimotor feedback

This paper presents a novel 32-channel bidirectional neural interface, capable of high voltage stimulation and low-power, low-noise neural recording. Current-controlled biphasic pulses are output with a voltage compliance of 9.25 V, user-configurable amplitude (max. 315 μA) & phase duration (max. 2 ms). The low-voltage recording amplifiers consume 23 μW per channel with programmable gain between 225–4725. Signals are 10-bit sampled at 16 kHz. Data rates are reduced by granular control of active recording channels, spike detection and event-driven communication, and repeatable multi-pulse stimulation configurations.

A fully-programmable neural interface for multi-polar, multi-channel stimulation strategies

This paper describes a novel integrated electrode interface for multi-polar stimulation of multi-electrode arrays. This interface allows for simultaneous stimulation using multiple electrodes configured as source or sink with different phase and amplitudes in order to perform field shaping inside the tissue. The system is designed in an high voltage 0.18 μm CMOS process with 8 channels. It features an output voltage swing of 16V and current up to 0.5mA for electrode impedences of up to 30kΩ which is suitable for cuff and cortical grid arrays. This electrode interface comprise a digital module which stores stimulation settings and operates the different electrode channels. Here we present the full system architecture and simulation results.

Towards a fully-integrated solution for capacitor-based neural stimulation

Charge-mode stimulation (ChgMS) is a relatively new method being explored in the field of electrical neural stimulation. One of the key challenges in such a system is to overcome charge sharing between the storage capacitor and the double layer capacitor in the Electrode-Electrolyte-Interface (EEI). In this work, this issue is overcome by using a second-generation negative current conveyor (CCII-) with a low current tracking error. The level of charge sharing in the circuit is expressed by a new figure of merit (charge delivery efficiency) introduced in this paper. The proposed system has a maximum power efficiency of 76.6% and a total power consumption of 270 μWper electrode for a target charge stimulus of 0.9 nC. Crucially, the system achieves a minimum charge delivery efficiency of 98.22%.

Compact standalone platform for neural recording with real-time spike sorting and data logging

OBJECTIVE Longitudinal observation of single unit neural activity from large numbers of cortical neurons in awake and mobile animals is often a vital step in studying neural network behaviour and towards the prospect of building effective brain-machine interfaces (BMIs). These recordings generate enormous amounts of data for transmission and storage, and typically require offline processing to tease out the behaviour of individual neurons. Our aim was to create a compact system capable of: (1) reducing the data bandwidth by circa 2 to 3 orders of magnitude (greatly improving battery lifetime and enabling low power wireless transmission in future versions); (2) producing real-time, low-latency, spike sorted data; and (3) long term untethered operation. APPROACH We have developed a headstage that operates in two phases. In the short training phase a computer is attached and classic spike sorting is performed to generate templates. In the second phase the system is untethered and performs template matching to create an event driven spike output that is logged to a micro-SD card. To enable validation the system is capable of logging the high bandwidth raw neural signal data as well as the spike sorted data. MAIN RESULTS The system can successfully record 32 channels of raw neural signal data and/or spike sorted events for well over 24 h at a time and is robust to power dropouts during battery changes as well as SD card replacement. A 24 h initial recording in a non-human primate M1 showed consistent spike shapes with the expected changes in neural activity during awake behaviour and sleep cycles. SIGNIFICANCE The presented platform allows neural activity to be unobtrusively monitored and processed in real-time in freely behaving untethered animals-revealing insights that are not attainable through scheduled recording sessions. This system achieves the lowest power per channel to date and provides a robust, low-latency, low-bandwidth and verifiable output suitable for BMIs, closed loop neuromodulation, wireless transmission and long term data logging.

A 890fJ/bit UWB transmitter for SOC integration in high bit-rate transcutaneous bio-implants

The paper presents a novel ultra low power UWB transmitter system for near field communication in transcutaneous biotelemetries. The system utilizes an all-digital architecture based on minising the energy dissipated per bit transmitted by efficiently encoding a packet of pulses with multiple bits and utilizing oscillator referenced delays. This is achieved by introducing a novel bi-phasic 1.65pJ per pulse UWB pulse generator together with a 72 μW DCO that provide a transmission bandwidth of 77.5 Mb/s with an energy efficiency of 890 fJ per bit from a 1.2 V supply. The circuit core occupies a compact silicon footprint of 0.026 mm2 in a 0.18μm CMOS technology.