Lijiu Ji

A fast locking charge-pump PLL with adaptive bandwidth

Design of bandwidth adaptive phase-locked loops (PLL) to achieve fast locking is presented in this paper. The proposed topology uses only one adaptive phase frequency detector (PFD) and controllable charge pumps to realize adaptive bandwidth scheme. With a SMIC standard 0.25mum 1P5M 2.5V CMOS logic process, the measured results show that the experimental chip has properties of fast locking less than 4 mus and low power consumption about 18mW

Low-power CMOS folding and interpolating ADC with a fully-folding technique

A 8-bit 150 MHz low-power CMOS folding and interpolating analog-to-digital converter with a fully-folding technique is designed in a 0.35 mum standard digital CMOS process. Folding circuits are not only used in fine converter but also in coarse one and in bit synchronization block to reduce the number of comparators for low power. A novel bit synchronization architecture based on folding circuits is presented. A low-power encoder using a novel arithmetic is adopted. The total power dissipation is merely 65 mW at a 3.3 V supply.

A low power high speed ROIC design for 1024×1024 IRFPA with novel readout stage

A low power high speed Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024 times 1024 image system. Ripple integration and readout scheme as well as highly efficient power management are introduced to this design in order to decrease total power. To further increase the readout speed while decrease the power dissipation, a novel readout stage is proposed and adopted in this circuit. By using the new structure, the ROIC achieves a data rate of 10 M/s per channel, with the total power dissipation of 56 mW.

A 64-bit lookahead carry chain in Inverted-Domino logic

Here we present a novel 64-bit adder carry chain design implemented in Inverted-Domino (iDomino) logic that is an improved style over conventional Domino for better performance. In the proposed scheme capacitances at output node are reduced and foot transistor in Domino logic is absorbed into clock tree to increase circuit speed. A 64-bit lookahead carry chain is constructed and HSPICE simulation in 0.25 /spl mu/m CMOS parameter shows that carry propagation can be done in less than 480 ps and a 20% speed enhancement over Domino is achieved.

Efficient encoding scheme for folding ADC

An efficient encoding scheme is proposed for folding ADC. In the encoder, XOR-OR encoding algorithm and dynamic domino circuit are adopted. A novel method for wide-range error correction and bit synchronization is presented. Simulation results show that the proposed encoder has several advantages: high speed, low power dissipation and small chip area.

CMOS folding and interpolating A/D Converter with differential compensative T/H circuit

A 450 MS/s, 6-bit CMOS folding and current-mode interpolating A/D Converter is designed in a 0.5 /spl mu/m standard digital CMOS process. A differential T/H circuit with the offset compensative amplifiers is proposed which can improve sample precision. The converters power dissipation is simulated as 190 mW from a 5 V supply. The latency between input and output is 2.5 clock cycles.

A CMOS TDI readout circuit for infrared focal plane array

A new structure 288 × 4 CMOS time delay and integration (TDI) readout integrated circuit (ROIC) is presented in this paper. The TDI function is implemented using an integration and storage circuit array and a charge amplifier with the advantages of low power and compact layout. An experimental chip has been designed and fabricated in 0.5 ¿m double-poly-three-metal CMOS technology. Bi-directional TDI, defective element deselection and two-gain option (1.015 pC/2.03 pC) functions have been realized in the experimental chip and measurement results at liquid nitrogen temperature indicated that all functions were correct and performance satisfied the requirement of long waveform IRFPA. The readout speed of each out can reach 5 MHz and the dynamic range is 75.6 dB.

A low power high speed readout circuit for 320×320 IRFPA

A low power high speed Readout Integrated Circuit(ROIC) design for 320 × 320 IRFPA is proposed in this paper. The ROIC operates as follows: after integration phase, voltages on column bus of odd rows and even rows are read out alternately. And the results are sampled and stored alternately on two sample capacitors added at the output point of column CSA. When sample capacitor for odd row samples and holds data, sample capacitor for even row works as feedback capacitor of output buffer so that voltage stored on sample capacitor can be read out directly. In this design, each column has one low power charge amplifier, and output buffers power is optimized. Besides, capacitance of sample capacitor is much larger than that of CSAs feedback capacitor, so the KTC noise is lower and the charge injection is suppressed while the output range is not impaired. This design is also applicable to window readout. The readout speed can reach 8MHz with power consumption lower than 50mW. A 320 × 320 ROIC with pixel size of 30 × 30 µm2 has been designed and fabricated with a 0.35 µm DPTM CMOS process under 5v supply voltage.

A low-noise interface circuit for MEMS vibratory gyroscope

A CMOS ASIC has been designed and implemented for readout and control of MEMS vibratory gyroscopes. A low noise design is achieved by using the technique of sinusoidal chopper stabilization with a chopping frequency of 2MHz, which will effectively suppress the low frequency noise. A closed loop control method in driving mode is presented. The Chip is fabricated in a 0.35µm standard CMOS process with an area of 2.5×2.5mm2. The test is performed with a vibratory gyroscope on the condition of closed-loop control, and the measurement result shows a detecting resolution of 6aF in 100Hz bandwidth from a single 5V supply.

A high efficient analog charge delay line for high performance CMOS readout integrated circuits with TDI function

A high efficient analog charge delay line (ACDL) is proposed in this paper. We can use these analog delay lines to realize high performance CMOS readout integrated circuits (ROIC) with time delay integration (TDI) function. A CMOS ROIC for 288 times 4 IRFPA were designed, manufactured, and tested. The chip has 4 video outputs, whose pixel frequency is 4~5MHz (for 384 times 288 format, its frame frequency can achieve 160 Hz). Test results show this chip has high dynamic range (>78 dB), high linearity (>99.5%), and high uniformity (96.8%). (TDI) function.