Yacong Zhang

A control and readout circuit with capacitive mismatch auto-compensation for MEMS vibratory gyroscope

In this paper, a control and readout circuit for MEMS vibratory gyroscope is described, including closed- loop driving axis and open-loop sensing axis. Capacitive mismatch auto-compensation has been implemented in this system to suppress the influence to the output due to the mismatch of gyroscope capacitors. The ASIC is fabricated in a 0.35um CMOS process. The test of the ASIC is performed with a MEMS vibratory gyroscope. The test result shows that the non-linearity is less than 0.1% within angular velocity range of -300°/s to 300°/s.

A CMOS TDI readout circuit for infrared focal plane array

A new structure 288 × 4 CMOS time delay and integration (TDI) readout integrated circuit (ROIC) is presented in this paper. The TDI function is implemented using an integration and storage circuit array and a charge amplifier with the advantages of low power and compact layout. An experimental chip has been designed and fabricated in 0.5 ¿m double-poly-three-metal CMOS technology. Bi-directional TDI, defective element deselection and two-gain option (1.015 pC/2.03 pC) functions have been realized in the experimental chip and measurement results at liquid nitrogen temperature indicated that all functions were correct and performance satisfied the requirement of long waveform IRFPA. The readout speed of each out can reach 5 MHz and the dynamic range is 75.6 dB.

A low-noise switched-capacitor interface for a capacitive micro-accelerometer

This paper presents a low-noise single-ended open-loop switched-capacitor interface circuit in 0.35μm CMOS technology for a comb structure micro-accelerometer. Using correlated double sampling, the low-frequency noise of the charge sensitive amplifier and the gain stage is suppressed, whereas the noise of the sensor charging reference voltage and the sample-and-hold circuit which follows the gain stage contributes considerably to the total output noise. In order to optimize the noise performance, an on-chip reference voltage generator and a dual-sample-and-hold circuit are designed. A detailed noise analysis of the two blocks is also presented. The fabricated prototype interface circuit achieves a measured capacitive sensitivity of 734mV/pF with an input equivalent noise floor of 0.41aF/√Hz and a dynamic range of 119.93dB over a 200Hz bandwidth at 1MHz sampling frequency.

A low noise, fast set-up low-dropout regulator in 65nm technology

Low noise, fast set-up low-dropout (LDO) regulators are critical for noise-sensitive analog blocks, such as ADCs, PLLs, and RF SoC, etc. This paper presents a two-stage LDO regulator with low output noise, fast set-up, and high power supply rejection ratio (PSRR), based on internal noise filter with a novel fast set-up module, which solves dc shift problems. The proposed LDO is fabricated in a standard 65nm CMOS process. Measurement showed that output noise rms voltage is about 50nV/rtHz ranging from 10Hz to 100 KHz, set-up time is less than 20us, and PSRR is 65B at 1 KHz and 54dB at 1MHz.

A high-voltage interface circuit for MEMS vibratory gyroscope

In this paper, a high-voltage interface circuit has been designed and implemented for MEMS gyroscope. Continuous-time charge sensitive amplifier with chopping stabilization technique is used in the conversion stage to achieve low noise performance. A closed driving loop for MEMS gyroscope which applying multiple supply voltages is presented. The chip is fabricated in a 0.35um 5V/12V high-voltage process. The test of the chip is performed with a MEMS vibratory gyroscope. The result shows that the driving output of the ASIC can ensure a stable oscillation in the driving axis.

A design of readout circuit for 384×288 uncooled microbolometer infrared focal plane array

A readout integrated circuit (ROIC) for uncooled infrared focal plane array (IRFPA) is presented in this paper. The ROIC is designed for a 384×288 detector array made of amorphous silicon microbolometers with a pixel-pitch of 35μm. A capacitive trans-impedance amplifier (CTIA) is used in each column to integrate the pixel signal. The design is tuned on a detailed theoretical analysis of the sensor signal and noise properties. The chip has been fabricated using a 0.35μm 2P4M CMOS process under 5V supply voltage. The ROIC can operate at a data rate of 7MHz, achieving a frame rate of 60Hz and the total power dissipation is less than 108m W. A 32×32 experimental chip has been tested.

A low power high speed readout circuit for 320×320 IRFPA

A low power high speed Readout Integrated Circuit(ROIC) design for 320 × 320 IRFPA is proposed in this paper. The ROIC operates as follows: after integration phase, voltages on column bus of odd rows and even rows are read out alternately. And the results are sampled and stored alternately on two sample capacitors added at the output point of column CSA. When sample capacitor for odd row samples and holds data, sample capacitor for even row works as feedback capacitor of output buffer so that voltage stored on sample capacitor can be read out directly. In this design, each column has one low power charge amplifier, and output buffers power is optimized. Besides, capacitance of sample capacitor is much larger than that of CSAs feedback capacitor, so the KTC noise is lower and the charge injection is suppressed while the output range is not impaired. This design is also applicable to window readout. The readout speed can reach 8MHz with power consumption lower than 50mW. A 320 × 320 ROIC with pixel size of 30 × 30 µm2 has been designed and fabricated with a 0.35 µm DPTM CMOS process under 5v supply voltage.

A high efficient analog charge delay line for high performance CMOS readout integrated circuits with TDI function

A high efficient analog charge delay line (ACDL) is proposed in this paper. We can use these analog delay lines to realize high performance CMOS readout integrated circuits (ROIC) with time delay integration (TDI) function. A CMOS ROIC for 288 times 4 IRFPA were designed, manufactured, and tested. The chip has 4 video outputs, whose pixel frequency is 4~5MHz (for 384 times 288 format, its frame frequency can achieve 160 Hz). Test results show this chip has high dynamic range (>78 dB), high linearity (>99.5%), and high uniformity (96.8%). (TDI) function.

A 14-bit differential-ramp single-slope column-level ADC for 640×512 uncooled infrared imager

This paper presents a low-power 14-bit column-level ADC for 640×512 size uncooled infrared imager. A novel differential-ramp single-slope (DRSS) structure is proposed in this work, which achieves 2x faster conversion speed and 3dB higher SNR performance compared with classical single-slope scheme. Moreover, a novel low-power area-saving result-consistent coarse-fine TDC scheme is proposed. The sensor with 17μm pixel pitch has been realized in 0.5 μm 2P3M CMOS process and applied in the thermal imaging system. Power consumption of per ADC is 120 μW. Measurement results demonstrate an average output RMS noise of 0.5LSB and a maximum nonlinearity of 3LSB.

A LOW-NOISE HIGH-VOLTAGE INTERFACE CIRCUIT FOR CAPACITIVE MEMS GYROSCOPE

This paper presents a high-voltage control and readout interface circuit implemented for capacitive Micro-Electro-Mechanic System (MEMS) gyroscope. A charge sensitive amplifier (CSA) with chopper technique is used to accomplish low-noise capacitive sensing. The stabilization of the closed drive loop is maintained by an auto gain controller (AGC) and an adjustable phase shifter. The outputs of the ASIC directly drive the gyroscope after buffered by an on-chip high-voltage level shifter. The chip is fabricated in a 0.35 um 5 V/12 V Bipolar, CMOS and DMOS (BCD) process. The test of the chip is performed with a MEMS vibratory gyroscope. The result shows that the Application Specific Integrated Circuit (ASIC) can ensure a stable oscillation in the drive axis, and the noise floor is 0.0015°/s/√Hz within 100 Hz.