Lilin Tian

Effective density-of-states approach to QM correction in MOS structures

Abstract MOS structure threshold voltage shift due to quantum mechanical effects (QMEs) has a substantial influence on deep-submicron MOSFET characteristics. However, its physical nature has not been thoroughly investigated and an analytical model is absent. In this paper, a numerical solution of the Schrodinger equation with parabolic potential well and an analytical solution with triangular well are compared, and the validity of the triangular well approximation is verified. Based on the calculation of the subband structure in the quantized region in a weak inversion regime, the concepts of surface layer effective density-of-states (SLEDOS) is proposed. Carrier distribution in subbands is then analyzed and physical base of MOSFETs Vth shift due to QMEs are discussed. The single subband occupation approximation used in earlier works is proved to be invalid and a new analytical threshold voltage (Vth) shift model due to QMEs including multisubband occupation is derived based on the concept of SLEDOS. The model reveals the physical nature of QMEs on Vth shift and gives consistent results with experiments and self-consistent calculation.

Scaling Theory for FinFETs Based on 3-D Effects Investigation

In this paper, the scaling theory of fin field-effect transistors (FinFETs) has been established by a 3D analytical solution and numerical simulation of Poissons equation in the channel region. Considering the impact of ionized dopant in channel and source/drain on the potential distribution, respectively, the 3D Poissons equation is analytically solved through the superposition method. Based on the analysis of the minimum channel potential, which is approximated from the evanescent mode, a useful and simple subthreshold-swing (S) model is proposed for design consideration. According to the derived scaling length, a FinFETs structure is superior in controlling short-channel effects (SCEs). A ratio of channel length to scaling length larger than three is required for optimization. Meanwhile, it is noticed that the gate material with relative dielectric constant of about ten could sufficiently suppress SCEs

Analytical charge-control and I-V model for submicrometer and deep-submicrometer MOSFETs fully comprising quantum mechanical effects

A new analytical current-voltage (I-V) model for submicrometer and deep-submicrometer metal-oxide-semiconductor field-effect transistors (MOSFETs) is developed based on a newly developed charge-control model for the metal-oxide-semiconductor structure. Threshold-voltage shift due to quantum mechanical effects, finite inversion layer thickness effects (inversion layer capacitance), as well as increased depletion layer charge density after the strong inversion point are incorporated in the model. Inversion layer charge density with respect to the gate voltage from depletion through weak inversion to strong inversion regions with smooth transition between different regions is given by one expression. Two-dimensional short channel effects such as channel length modulation, drain-induced barrier lowering, mobility degradation, and carrier velocity saturation, as well as polysilicon depletion effects are included in the I-V model. Model results are compared with both numerical results of carrier sheet density and surface potential in the channel, and experimental results of I-V data for submicrometer and deep-submicrometer MOSFETs down to 0.09-/spl mu/m effective gate length and the accuracy of the model are demonstrated.

Analytical Electron-Mobility Model for Arbitrarily Stressed Silicon

It was experimentally and numerically indicated that both the valley splitting and effective-mass variation contribute to the stress-induced enhancement of electron mobility in the MOSFET channel. In this paper, an analytical electron-mobility model for arbitrarily strained silicon is presented. The electron-mobility model includes the strain effects of both the effective-mass variation and valley degeneration. The expression of strained conduction band used in the analytical model is based on the theory and accords well with numerical results of nonlocal empirical pseudopotential method (EPM). By using the mobility model, mobilities under different stresses are investigated.

Patterned buried oxide layers under a single MOSFET to improve the device performance

A novel quasi-silicon-on-insulator (Q-SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) has been successfully fabricated, where the drain and source regions were positioned on the patterned buried oxide (BOX) layers while the channel region was left connected to the substrate. The high-quality BOX layers patterned under a single MOSFET were formed by the masked separation by implantation of oxygen technique. The electrical and thermal properties of such a novel Q-SOI device were investigated and the results demonstrated that this Q-SOI device has improved performances over the SOI counterpart because of suppression of the floating-body and self-heating effects.

Modified Airy function method for modeling of direct tunneling current in metal–oxide–semiconductor structures

Using a modified Airy function (MAF) to solve the Schrodinger equation in the whole metal–oxide–semiconductor structure, a fully quantum-mechanical model of direct tunneling current from an inverted p-Si substrate through ultrathin oxides is presented. The effects of tunneling on the electrostatic potential and the distribution of electrons are also included when self-consistently solving the Schrodinger and Poisson equations in silicon. Due to the semianalytical nature of the MAF method, the model has high efficiency. Model results are compared with experimental data and show excellent agreement. Moreover, an approximately linear relationship between the logarithm of the direct tunneling current and oxide thickness is found out.

A new charge model including quantum mechanical effects in MOS structure inversion layer

Abstract Based on the analysis of the distribution of inversion layer carriers in MOS structure, the concept of surface layer effective density-of-states (SLEDOS) is proposed. Then a new charge control model suitable for both semi-classical and quantum mechanical theory is established in which the effects of inversion layer carrier distribution on surface potential are included. In this model, a newly developed efficient iteration method is introduced, which has high efficiency and satisfied stability. Based on the model, the effects of quantum mechanical effects (QMEs) on inversion layer charge density both in weak and strong inversion regions and the surface potential are studied. Model results are compared with the self-consistent solutions of Schrodinger and Poisson equations, which proves the high accuracy of the new model.

Measurement of thermal conductivity of buried oxides of silicon-on-insulator wafers fabricated by separation by implantation of oxygen technology

In this work, an improved method for measuring the thermal conductivity of buried oxides of a silicon-on-insulator (SOI) wafer is proposed which is simple and effective. Using this method, the thermal conductivity of thin buried oxides with different SOI wafer thicknesses fabricated by separation by implantation of oxygen (SIMOX) technology is measured. It is found that at least in the range of thickness not less than 55 nm, the classically defined thermal conductivity of the SIMOX oxide remains constant (i.e., no size effect is observed) and is equal to 1.06 W m−1 K−1, which is smaller than the 1.4 W m−1 K−1 normally used value in device engineering. The boundary thermal resistance between the Si/SiO2 interface for SIMOX technology is measured accurately here. The results show that this boundary resistance cannot be neglected in calculation of the thermal resistance of SOI devices especially in the case of thinner back oxide.

Simulation of Layout-Dependent STI Stress and Its Impact on Circuit Performance

The impact of STI stress with layout dependency on circuit performance is investigated. A 3D stress simulator has been developed using finite element method, which considers both the layout design and process information (PDK). The mobility change due to stress is included in the transistor modeling for circuit simulation. The circuit performance can thus be analyzed with nonlocal stress. As a test case, a buffered SR flip-flop was simulated with and without STI stress considered. It can be seen that STI stress has non-negligible influence on the circuit performance.

Fabrication of self-aligned drain and source on insulator MOSFET with dielectric pocket by local SIMOX technology

In this work, a method to fabricate SA-DSOI MOSFET with dielectric pocket has been presented. Dielectric pocket and BOX are realized by local SIMOX technology. This novel structure results in good SCE and SHE suppression and higher speed performance, which is very important in nanoscale device design. With this novel self-aligned process, DSOI MOSFET can be scaled down to nano-scale and becomes a promising device.