Lilly Huang

Novel Current Sharing Schemes for Multiphase Converters with Digital Controller Implementation

Multiphase converters require a current sharing loop to maintain equal or desired current sharing between phases or paralleled modules. Conventional current sharing schemes are based on sensing each phase current to provide the current information to the control loop. Such schemes have disadvantages including the fact that they operate to generate a pre-set sharing ratio that is independent of converter efficiency value, they are highly affected by the sensing accuracy of each phase, and they require large associated sensing circuitries and off-line calibration. In this paper, new efficiency based current sharing concepts and schemes are proposed and discussed to eliminate or reduce the disadvantages of conventional schemes. The proposed concepts are based on dynamically maximizing the efficiency (minimizing power losses) of the converter to achieve the optimum current sharing ratio. They also provide schemes that are independent of sensing accuracy and require a reduced number of sensors and associated circuitries. The proposed schemes can be used for current sharing as stand-alone designs or can be combined with conventional schemes to achieve online current sharing loop calibration. Digital controller implementation is presented utilizing flexibility and other advantages of digital controllers. Experimental results are presented to support the theoretical analysis.

Adaptive Digital Controller and Design Considerations for a Variable Switching Frequency Voltage Regulator

An auto-tuning adaptive digital controller with maximum efficiency point tracking to optimize dc-dc converter switching frequency is presented in this paper. The adaptive-frequency-optimization (AFO) controller adjusts the dc-dc converter switching frequency while tracking the converter minimum input power (maximum efficiency) point under variable operation conditions of the power converter. The AFO digital controller continuously finds the optimum switching frequency that will result in minimum total power loss while converter parameters and conditions vary. Moreover, the presented controller addresses the issues that are associated with implementing variable switching frequency in digital controllers, including limit cycle oscillation and possible performance degradation, by using a dynamic algorithm to maintain converter system stability under variable switching frequency operation. In this paper, the proposed controller is discussed, analyzed, and its digital control algorithms and experimental results are presented.

Efficiency-Based Auto-Tuning of Current Sensing and Sharing Loops in Multiphase Converters

Multiphase converters require a current-sharing loop to maintain equal or desired current sharing between phases or paralleled modules. The current-sharing loop is highly sensitive to current-sensing accuracy. In this letter, a method is presented to achieve auto-tuning of the current-sharing loop in multiphase converters while adaptively calibrating the current sensing based on power conversion efficiency. This is achieved without the need for a precise calibration reference or resistor and with no dependency on sensing accuracy. A digital controller implementation of the method is described and experimental results are obtained for a 0.84 V/30 A two-phase buck voltage regulator.

Window-Masked Segmented Digital Clock Manager-FPGA-Based Digital Pulsewidth Modulator Technique

This paper presents a new digital pulsewidth modulator (DPWM) architecture for field programmable gate array (FPGA)-based systems. The design of the proposed DPWM architecture is based on fully utilizing the digital clock manager (DCM) resources available on new FPGA boards. Furthermore, this architecture will also window-mask the DCM operation to only a portion of the switching period in order to decrease power dissipation. This proposed digital modulator technique allows for higher DPWM resolution with lower power consumption, the primary barrier to high switching frequency operation. The presented technique relies on power-optimized resources already existing on new FPGAs, and benefits from the inherit phase-shifting properties of the DCM blocks, which help in simplifying the duty cycle generation. The architecture can be applied to achieve different numbers of bits for the DPWM resolution designed for different dc-dc applications. The suggested architecture is first simulated, implemented, and experimentally verified on a Virtex-4 FPGA board.

Highly Efficient VRM For Wide Load Range with Dynamic Non-Uniform Current Sharing

Multiphase converters are widely used especially in powering high-current loads. These converters are conventionally designed with symmetric phases and equal/uniform current sharing. This paper presents a multiphase VRM utilizing the concept of dynamic non-uniform current sharing between non-uniform phases. It is shown in this paper that high efficiency conversion can be achieved over wider load range with non-uniform phase design in multiphase converters and by utilizing the control scheme of dynamically varied non-uniform current sharing ratio between the interleaved phases. It is also shown that the proposed concept does not necessarily cause the increase in the size and cost of VRM design. The concept can be further expanded to the designs of other power stages such as AC-DC and PFC converters, bus converters and isolated or non-isolated converters. Theoretical and experimental results are provided in this paper, and they are compared with conventional symmetric designs with uniform current sharing.

Segmented Digital Clock Manager- FPGA based Digital Pulse Width Modulator Technique

A new digital pulse width modulator (DPWM) design for a field programmable gate array (FPGA) based systems is presented in this paper. The proposed architecture fully utilizes the digital clock manager (DCM) resources available on new FPGA boards. The proposed segmented DCM DPWM is a digital modulator architecture with low power that allows for high switching frequency operation. It relies on the power-optimized resources already existing on new FPGAs. The inherit phase shifting properties of the DCM blocks simplify the duty cycle generation. The architecture can be applied to achieve various number of bits for the DPWM resolution, and is implemented and verified experimentally on a Virtex4 FPGA board.

Design Considerations and Dynamic Technique for Digitally Controlled Variable Frequency DC-DC Converter

A dynamic algorithm to avoid limit cycle oscillation problems and to improve stability in digitally controlled power converters with variable switching frequency operation is presented in this paper. Employing Variable switching frequency at light loads is one way to improve the efficiency of DC-DC converters. However, varying the switching frequency digitally introduces additional considerations that do not exist in variable frequency analog controllers. In this paper a dynamic algorithm to maintain system stability and dynamics at different switching frequencies and to avoid limit cycle oscillation problems is discussed and experimentally verified.

Adaptive Variable Switching Frequency Digital Controller Algorithm to Optimize Efficiency

An adaptive digital controller with maximum efficiency point tracking to optimize DC-DC converter switching frequency is presented in this paper. The adaptive-frequency-optimization (AFO) method changes the DC-DC converter switching frequency while tracking the converter minimum input power (maximum efficiency) point under variable conditions including variable load and variable input voltage. The AFO digital controller continuously finds the optimum switching frequency that result in the minimum total loss while converter parameters and conditions vary. In this paper, the AFO method is discussed analyzed and its digital control algorithm and experimental implementation are presented.

Power Converter with Gradient Power Architecture and Non-Uniform Current Sharing

A gradient power architecture concept with non-uniform current/power sharing is presented in this paper. A voltage regulator with this concept is designed, analyzed, and experimented. This scheme results in improved efficiency especially at lighter loads and the ability to control steady-state and dynamic performance especially when some of the phases are turned OFF at lighter loads

A Highly Efficient Reconfigurable Charge Pump Energy Harvester With Wide Harvesting Range and Two-Dimensional MPPT for Internet of Things

A monolithic microwatt-level charge pump energy harvester is proposed for smart nodes of Internet of Things (IOT) networks. Due to the variation of the available voltage and power in IOT scenarios, the charge pump was optimized by the proposed architecture and circuit level innovations. First, a reconfigurable charge pump is introduced to provide the hybrid conversion ratios (CRs) as 1[1/3]× up to 8× for minimizing the charge redistribution loss. Second, the reconfigurable feature also dynamically tunes to maximum power point tracking (MPPT) with the frequency modulation, resulting in a two-dimensional (2-D) MPPT. Therefore, the voltage conversion efficiency (VCE) and the power conversion efficiency (PCE) are enhanced and flattened. Third, the constanton-time (COT) scheme from the regulation part was reused with the proposed MPPT arbiter as a sensing approach, which eliminates the conventional power hungry current sensor. The proposed energy harvester is capable of harvesting various energy sources, such as a photovoltaic (PV) cell and a thermoelectric generator (TEG), with a wide input range from 0.45 to 3 V and a regulated 3.3 V output voltage for the IOT smart nodes. Measured results showed that the harvester achieved a flattened and improved PCE as high as 89% for ultra-low power operation capability below 50 μW.