Wisam Al-Hoor

Efficiency Improvement of Grid-Tied Inverters at Low Input Power Using Pulse-Skipping Control Strategy

A pulse-skipping control strategy is proposed to improve efficiency of grid-tied inverters at light loads. To maximize the efficiency of pulse-skipping operation mode, three key parameters are identified and optimized based on a loss model, which is developed to find the maximal efficiency points using a 3-D search technique. A 200-W prototype inverter was setup to verify the proposed control strategy. The experimental results show that the proposed pulse-skipping control strategy greatly improves the inverters efficiency at light loads and match the simulation results fairly well, thus, validating the proposed optimization method for pulse-skipping operation.

Efficiency improvement of grid-tied inverters at low input power using pulse skipping control strategy

Pulse skipping control strategy is applied to improve efficiency of grid-tied inverter at light load. To maximize the efficiency of pulse skipping operation mode, three key parameters are identified and can be optimized based on a loss model, which is developed to find the maximal efficiency points using three-dimension searching technique. To reduce the potential of pulsating on the power grid, the synchronization of the power pulse to the grid is addressed by varying the DC bus voltage window, namely varying the upper and lower DC voltage limits. A 200W prototype is setup to verify the proposed strategy. The experimental results show that the proposed strategy greatly improves the efficiency at light load and match the simulation results fairly well, thus verifying the validity of the proposed optimization method for pulse skipping.

Adaptive Digital Controller and Design Considerations for a Variable Switching Frequency Voltage Regulator

An auto-tuning adaptive digital controller with maximum efficiency point tracking to optimize dc-dc converter switching frequency is presented in this paper. The adaptive-frequency-optimization (AFO) controller adjusts the dc-dc converter switching frequency while tracking the converter minimum input power (maximum efficiency) point under variable operation conditions of the power converter. The AFO digital controller continuously finds the optimum switching frequency that will result in minimum total power loss while converter parameters and conditions vary. Moreover, the presented controller addresses the issues that are associated with implementing variable switching frequency in digital controllers, including limit cycle oscillation and possible performance degradation, by using a dynamic algorithm to maintain converter system stability under variable switching frequency operation. In this paper, the proposed controller is discussed, analyzed, and its digital control algorithms and experimental results are presented.

Window-Masked Segmented Digital Clock Manager-FPGA-Based Digital Pulsewidth Modulator Technique

This paper presents a new digital pulsewidth modulator (DPWM) architecture for field programmable gate array (FPGA)-based systems. The design of the proposed DPWM architecture is based on fully utilizing the digital clock manager (DCM) resources available on new FPGA boards. Furthermore, this architecture will also window-mask the DCM operation to only a portion of the switching period in order to decrease power dissipation. This proposed digital modulator technique allows for higher DPWM resolution with lower power consumption, the primary barrier to high switching frequency operation. The presented technique relies on power-optimized resources already existing on new FPGAs, and benefits from the inherit phase-shifting properties of the DCM blocks, which help in simplifying the duty cycle generation. The architecture can be applied to achieve different numbers of bits for the DPWM resolution designed for different dc-dc applications. The suggested architecture is first simulated, implemented, and experimentally verified on a Virtex-4 FPGA board.

Segmented Digital Clock Manager- FPGA based Digital Pulse Width Modulator Technique

A new digital pulse width modulator (DPWM) design for a field programmable gate array (FPGA) based systems is presented in this paper. The proposed architecture fully utilizes the digital clock manager (DCM) resources available on new FPGA boards. The proposed segmented DCM DPWM is a digital modulator architecture with low power that allows for high switching frequency operation. It relies on the power-optimized resources already existing on new FPGAs. The inherit phase shifting properties of the DCM blocks simplify the duty cycle generation. The architecture can be applied to achieve various number of bits for the DPWM resolution, and is implemented and verified experimentally on a Virtex4 FPGA board.

Design Considerations and Dynamic Technique for Digitally Controlled Variable Frequency DC-DC Converter

A dynamic algorithm to avoid limit cycle oscillation problems and to improve stability in digitally controlled power converters with variable switching frequency operation is presented in this paper. Employing Variable switching frequency at light loads is one way to improve the efficiency of DC-DC converters. However, varying the switching frequency digitally introduces additional considerations that do not exist in variable frequency analog controllers. In this paper a dynamic algorithm to maintain system stability and dynamics at different switching frequencies and to avoid limit cycle oscillation problems is discussed and experimentally verified.

Adaptive Variable Switching Frequency Digital Controller Algorithm to Optimize Efficiency

An adaptive digital controller with maximum efficiency point tracking to optimize DC-DC converter switching frequency is presented in this paper. The adaptive-frequency-optimization (AFO) method changes the DC-DC converter switching frequency while tracking the converter minimum input power (maximum efficiency) point under variable conditions including variable load and variable input voltage. The AFO digital controller continuously finds the optimum switching frequency that result in the minimum total loss while converter parameters and conditions vary. In this paper, the AFO method is discussed analyzed and its digital control algorithm and experimental implementation are presented.

Variable- Step-Size Auto-Tuning Algorithm for Digital Power Converter with Variable-Switching-Frequency

This paper presents the analysis and implementation of a digital controller with adaptive auto- tuning algorithm that has a variable step size to track and detect the optimum switching frequency for a DC-DC converter. The algorithm is theoretically analyzed and developed based on buck DC-DC converter loss model and behavior and directed towered improving the convergence speed and accuracy of the adaptive loop by adjusting the converter switching frequency with variable step size. Simulation results are presented for the developed algorithm under variable conditions. Future experimental work is also discussed.

Multivariable adaptive efficiency optimization digital controller

A multivariable adaptive digital controller to optimize DC-DC converter switching frequency and dead- time at the same time, for maximum efficiency under variable conditions, is presented in this paper. The multivariable adaptive digital controller (MVAC) adaptively adjusts the DC-DC converter switching frequency and dead-time while tracking the converter minimum input power (maximum efficiency) point under variable conditions including variable load and variable input voltage. In this paper, the MVAC method is discussed analyzed and its digital control algorithm and experimental results are presented.

DSP-based stable control loops design for a single stage inverter

The design of stable DSP-based controller for a new single stage inverter architecture with solar energy input is discussed in this paper. The proposed architecture uses two dependent control loops to track the maximum available power of a solar array source, and to supply a sinusoidal current to the utility grid. If not well designed, the control loops in this inverter configuration suffer from instability when operating at different regions of the solar array power curve, namely the Right Hand Side region (RHS) and the Left Hand Side region (LHS). This paper presents a mathematical analysis to the source of instability, and proposes a robust controller for stable system design. Experimental results are presented to verify the validity of the designed controller.