Vaibhav Vaidya

A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS

A fully on-die, digitally controlled, 500MHz switching, 250mA rated output buck Voltage Regulator (VR) implemented in 22nm Tri-Gate CMOS is presented. The silicon measured a peak efficiency of 68% and consumed an area of 0.6mm2 (without output decoupling) with a power density of about 410 mW/mm2. The paper also demonstrates a controller bandwidth of 43MHz; the highest reported to date for any digital controller, resulting in output voltage ramp rates as high as 10V/μsec.

Universal Current-Mode Control Schemes to Charge Li-Ion Batteries under DC/PV Source

A pair of universal current mode control schemes for charging a Li-ion battery for mobile applications are discussed in this paper. The peak-current mode control schemes, based on a single control loop, is universal because it is designed with a single-stage buck charger for both a conventional wall adapter dc source as well as a solar photovoltaic (PV) module of comparable specifications. The charging schemes remove the need for an extra MPPT (maximum power point tracking) power converter stage. This control scheme is non-linear and incorporates all possible scenarios: mode of operation of a battery, current charging rate and power characteristic of input source. The algorithm uses need-based MPPT and ensures minimal battery discharge, and also uses minimum number of sense variables in the circuit. The methods differ in the way MPPT is implemented: perturb and observe (P&O) and fractional open circuit voltage. Simulation results demonstrating battery charge profile, validity of the algorithm under varying insolation conditions and platform workloads are presented, along with a discussion of the trade-offs of the two methods. Proof-of-concept hardware results are also provided.

Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS

Active conduction modulation techniques are demonstrated in a fully integrated multi-ratio switched-capacitor voltage regulator with hysteretic control, implemented in 22nm tri-gate CMOS with high-density MIM capacitor. We present (i) an adaptive switching frequency and switch-size scaling scheme for maximum efficiency tracking across a wide range voltages and currents, governed by a frequency-based control law that is experimentally validated across multiple dies and temperatures, and (ii) a simple active ripple mitigation technique to modulate gate drive of select MOSFET switches effectively in all conversion modes. Efficiency boosts upto 15% at light loads are measured under light load conditions. Load-independent output ripple of <;50mV is achieved, enabling fewer interleaving. Testchip implementations and measurements demonstrate ease of integration in SoC designs, power efficiency benefits and EMI/RFI improvements.

Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS.

Switch conductance modulation techniques are demonstrated in a fully integrated multi-ratio switched-capacitor voltage regulator with hysteretic control, in 22 nm tri-gate CMOS with high-density MIM capacitor. We present (i) an adaptive switch-size scaling scheme for maximum efficiency tracking across a wide range of voltages and currents, governed by a frequency-based control law that is experimentally validated across multiple dies and temperatures and, (ii) a simple active ripple mitigation technique that modulates the gate drive of select MOSFET switches effectively in all conversion modes. Efficiency improvements up to 15% are measured under low output voltage and load conditions. Load-independent output ripple of <;50 mV is achieved, enabling reduced interleaving. Test chip implementations and measurements demonstrate ease of integration in SoC designs, power efficiency benefits and EMI/RFI improvements.

13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications

To benefit from Moores law and minimize form-factor and active power consumption, digital-rich SoCs should be integrated in the most advanced technology node. If the transceiver is integrated in a different technology node, multi-chip solutions are required, increasing system cost and form-factor. Traditional radio architectures require extensive use of high-quality passives, which might use large silicon area or not be available due to process limitations. Fast time to market also demands quicker design cycles, where extensive use of standard digital cells and even automated place-and-route tools for layout is preferred [1]. The proposed transmitter leverages a polar architecture with synthesized digital-to-time converter (DTC) wideband phase modulator, an all-digital PLL and a digital PA with matching network implemented on a flip-chip package to enable single-chip integration in 14nm trigate/finFET technology for IoT and wearable SoCs.

A 0.4V∼1V 0.2A/mm 2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS

Monolithic integration of Voltage Regulators (VR) is challenging given the inherent lack of scalability of inductor. Circuit techniques to reduce inductor size are attractive to increase power density and scalability. This paper presents a 70~72% efficient, 500MHz digitally controlled 3-level Buck VR with a fully on-die spiral inductor implemented on 22nm Tri-Gate CMOS with MIM capacitors. The advantages of the 3-level converter for wide range Dynamic Voltage & Frequency Scaling (DVFS) over traditional solutions like linear regulators & Buck VRs are demonstrated.