Ling Du

A 10-bit 100MS/s subrange SAR ADC with time-domain quantization

This paper presents a 10-bit subrange successive approximation register analog-to-digital converter (SAR ADC). A 3.5-bit time-domain coarse ADC converts the analog input to the time delay of two pulse signals and a time-to-digital converter (TDC) is used to quantize the delay. The coarse ADC controls the switching of the higher 3-bit capacitors in the digital-to-analog converter (DAC). A 7-bit SAR controls the remaining capacitors. The 1-bit redundancy corrects the linearity and mismatch error of the coarse ADC. The proposed 10-bit 100MS/s ADC is designed in a 65nm CMOS technology with 1.2V power supply. Simulation results show that this design achieves 59.7dB SNDR and consumes 2.69mW. The figure-of-merit (FOM) is 34.2fJ/conversion-step.

A 10-bit 100MS/s time domain Flash-SAR ADC

This paper presents a 10-bit subranging successive approximation register analog-to-digital converter (SAR ADC). A 3.5-bit time-domain coarse ADC converts the analog input to the time delay of two pulse signals and a time-to-digital converter (TDC) is used to quantize the delay. The coarse ADC controls the switching of the higher 3-bit capacitors in the digital-to-analog converter (DAC). A 7-bit SAR controls the remaining capacitors. The 1-bit redundancy corrects the linearity and mismatch error of the coarse ADC. The proposed 10-bit 100MS/s ADC is designed in a 65nm CMOS technology with 1.2V power supply. Simulation results show that this design achieves 59.7dB SNDR and consumes 2.69mW. The figure-of-merit (FoM) is 34.2fJ/conversion-step.

A DITHERING TECHNIQUE FOR SHA_LESS PIPELINED ADC

A dithering technique for pipelined analog-to-digital converter (ADC) without sample-and-hold amplifier (SHA) is proposed in this paper. The dither signals are injected to the output of the first stage multiplying digital-to-analog converter (MDAC) and the input of the first stage Sub_ADC simultaneously. The equivalent input voltage of the first stage Sub_ADC is consistent with that of the first stage MDAC with dither. To subtract the dither signal precisely, all of the dither signals are quantified by the ADC itself before normal conversion, and the digital codes representing dither signals are stored. During normal conversion, a dither signal selected randomly is added to the analog input and the corresponding digital code is subtracted from the digital output. The proposed dithering technique is verified by behavior simulation. The simulation results show that the spurious free dynamic range (SFDR) is improved effectively and the degradation of signal-to-noise ratio (SNR) can be minimized.

A fast successive approximation calibration technique with bypass window in DACs

This paper presents a successive approximation calibration technique with bypass window used in current-steering DACs to reduce calibration numbers. It utilizes bypass window technique to select switching sequences to skip several conversion steps. A behavioral model of 14-bit (7+7) segmented DACs was implemented under 40/55/180nm CMOS process. According to the fast SAC for MSB current sources, the calibration time is reduced obviously and the DNL and INL are both smaller than 0.5LSB compared with traditional SAC.

A digital background calibration technique for SAR ADC based on capacitor swapping

A digital background calibration technique that compensates for capacitor mismatches is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in the SAR ADC based on tri-level switching. The termination capacitor in the digital-to-analog converter is considered as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation result shows that the signal-to-noise and distortion ratio is improved from 57.1 dB to 72.0 dB and the spurious free dynamic range is improved from 62.0 dB to 82.6 dB.

A process variation insensitive bandgap reference with self-calibration technique

A process variation insensitive bandgap reference with self-calibration is presented. The initial accuracy of the bandgap reference is improved with self-calibration. The offset voltage caused by components mismatch due to process variation is averaged with a 6-bit resistor trimming array and the code for trimming is generated by the circuit itself. The 3σ inaccuracy of the bandgap reference decreases from ±12.6% to ±1.0% with the self-calibration. The circuit consumes 43.5μW and occupies 0.025mm2 in a standard 65nm 1P6M CMOS technology.

The Impact of Gate Leakage Current on PLL in 65 nm Technology: Analysis and Optimization

For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phase- locked loop (PLL) is analyzed and modeled. A voltage -to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on Vctrl induced by the gate leakage current. The side effects induced by the V-to-V circuit are described and optimized either. The PLL design is based on a standard 65 nm CMOS technology with a 1.8 V power supply. Simulation results show that 97 % ripple voltage is smoothed at 216 MHz output frequency. The RMS and peak-to-peak jitter are 3 ps and 14.8 ps, respectively