Shuangyi Wu

A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs

A digital calibration scheme is proposed to minimize the timing mismatch in time-interleaved analog-to-digital converters (TIADCs). First, the scheme is to subtract the outputs from adjacent channel ADCs and to utilize the expectations of the absolute value of the subtracted results to represent the actual sampling time interval. The timing mismatch is recognized by comparing these expectations. The obtained information is fed back to adjust variable delay buffers, thus reducing the timing mismatch. The application of this scheme to a 12-bit 1.6 GS/s four-channel TIADC is demonstrated. Simulation results show that with an input signal whose bandwidth is limited to the Nyquist frequency, the proposed timing mismatch calibration scheme is effective and capable of reducing the mismatch to the minimum. Compared with traditional calibration schemes, the proposed scheme is more feasible to implement and consumes less power and chip area.

An 8-Bit 250MSPS Modified Two-Step ADC

Based on conventional two-step ADC principle, an 8-bit 250MSPS modified two-step ADC is proposed to reduce power dissipation. It is realized by applying triple-stage comparison for the number reduction of comparators, substituting new reference region selecting logic (RRSL) blocks for sub-DACs and adding sample/hold (S/H) circuit to replace residue amplifier. Simulated with SMIC O.35 mum/3.3 V AMS Si-CMOS process models, the results are shown that on the condition of realizing 250MSPS, the ADC achieves DNL<plusmn0.4LSB, INL<plusmn.5LSB, SFDR 59.2 dB at Nyquist frequency, only 85 mW power dissipation and 1.2times0.8 mm2 layout area. The ADC system architecture is to be employed in the field of high-speed low-power mixed-signal processing

A 10-bit 100MS/s subrange SAR ADC with time-domain quantization

This paper presents a 10-bit subrange successive approximation register analog-to-digital converter (SAR ADC). A 3.5-bit time-domain coarse ADC converts the analog input to the time delay of two pulse signals and a time-to-digital converter (TDC) is used to quantize the delay. The coarse ADC controls the switching of the higher 3-bit capacitors in the digital-to-analog converter (DAC). A 7-bit SAR controls the remaining capacitors. The 1-bit redundancy corrects the linearity and mismatch error of the coarse ADC. The proposed 10-bit 100MS/s ADC is designed in a 65nm CMOS technology with 1.2V power supply. Simulation results show that this design achieves 59.7dB SNDR and consumes 2.69mW. The figure-of-merit (FOM) is 34.2fJ/conversion-step.

A 10-bit 100MS/s time domain Flash-SAR ADC

This paper presents a 10-bit subranging successive approximation register analog-to-digital converter (SAR ADC). A 3.5-bit time-domain coarse ADC converts the analog input to the time delay of two pulse signals and a time-to-digital converter (TDC) is used to quantize the delay. The coarse ADC controls the switching of the higher 3-bit capacitors in the digital-to-analog converter (DAC). A 7-bit SAR controls the remaining capacitors. The 1-bit redundancy corrects the linearity and mismatch error of the coarse ADC. The proposed 10-bit 100MS/s ADC is designed in a 65nm CMOS technology with 1.2V power supply. Simulation results show that this design achieves 59.7dB SNDR and consumes 2.69mW. The figure-of-merit (FoM) is 34.2fJ/conversion-step.

A DITHERING TECHNIQUE FOR SHA_LESS PIPELINED ADC

A dithering technique for pipelined analog-to-digital converter (ADC) without sample-and-hold amplifier (SHA) is proposed in this paper. The dither signals are injected to the output of the first stage multiplying digital-to-analog converter (MDAC) and the input of the first stage Sub_ADC simultaneously. The equivalent input voltage of the first stage Sub_ADC is consistent with that of the first stage MDAC with dither. To subtract the dither signal precisely, all of the dither signals are quantified by the ADC itself before normal conversion, and the digital codes representing dither signals are stored. During normal conversion, a dither signal selected randomly is added to the analog input and the corresponding digital code is subtracted from the digital output. The proposed dithering technique is verified by behavior simulation. The simulation results show that the spurious free dynamic range (SFDR) is improved effectively and the degradation of signal-to-noise ratio (SNR) can be minimized.

Design and realization of a voltage detector based on current comparison in a 40nm technology

A design of low-power voltage detector (VD) based on current comparison technology is presented. This VD samples the power supply voltage and converts the sampled voltage to a current which will be compared with a reference. The current comparison technology simplifies the design without use of the resistor string and voltage comparators, and thus reduces the core area. The VD detects three thresholds successively while keeping only one detecting portion working at a time to minimize power consumption. The VD is designed and realized in a standard 40nm process. The measurement result agrees well with designed parameters with 3s variations less than 100mV. Meanwhile, the power consumption keeps lower than 10μW.

An improved switched-emitter-follower for high-resolution GS/s-rate track-and-hold amplifiers

This paper presents an improved switched-emitter-follower for high-resolution GS/s-rate track-and-hold amplifier. A dummy switched-emitter-follower is introduced to compensate track-mode nonlinearity. And a clamping amplifier is utilized to reduce hold-mode feedthrough in high sample rate. The proposed switched-emitter-follower was chip verified in a 12bit 1GS/s THA based on 0.18pm SiGe BiCMOS process. Post-layout simulations show that the proposed THA achieves a spurious free dynamic range of 71 dB for 497 MHz input frequency at 1 GS/s rate. Operating from a 3.3V supply, the power dissipation of the proposed switched-emitter-follower is 156mW.

A fast successive approximation calibration technique with bypass window in DACs

This paper presents a successive approximation calibration technique with bypass window used in current-steering DACs to reduce calibration numbers. It utilizes bypass window technique to select switching sequences to skip several conversion steps. A behavioral model of 14-bit (7+7) segmented DACs was implemented under 40/55/180nm CMOS process. According to the fast SAC for MSB current sources, the calibration time is reduced obviously and the DNL and INL are both smaller than 0.5LSB compared with traditional SAC.

An inductive peaking technology for high-speed MIPI receiver bandwidth expanding in a 90 nm CMOS process

An inductive peaking technology is proposed in this paper for improving receiver bandwidth. A N/PMOS cross biasing active inductor and negative Miller capacitance are introduced to provide inductive peaking around the amplifier bandwidth. According to the simulation and experimental results within a MIPI receiver under 1.2V CMOS 90nm process, the inductive peaking technology increases the bandwidth of the preamplifier in the MIPI PHY circuit from 1.05GHz to 2.09GHz. As a results, the PHY circuit which employs the inductive peaking amplifier consumes only 4mW power for transferring 1Gbps data signal with 70mV differential amplitude to 1.2V CMOS level.

Design of a high resolution multi-phase clock generator based on DLL

This paper presents a multi-phase clock generator with high resolution based on DLL. By employing the static phase error, fine tuning step is achieved with the simplest DLL structure. The charging current and discharging current of charge pump (CP) are set to be unequal to get static phase error. The simulation results show the delay step resolution of the generator with 400MHz input is 5ps and the control voltage (VC) is 0.5V when DLL is locked.