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High PSRR and high-order curvature-compensated bandgap voltage reference

Based on the principle of piecewise compensation, a new high-order curvature compensated method of bandgap reference is presented in this paper. This method focuses on forming multiple local extrema of the curve of reference voltage instead of single valley or peak in the entire operating temperature range, which improves the temperature independence significantly. It has a temperature coefficient in the −40°C to 135°C range of 0.58 ppm/°C simulated in 0.5 μm CMOS process. Adopting the error amplifier with improved PSRR, the PSRR is −95.4dB at dc and −56dB at 100KHz with 5V power supply.

A 10-bit 100MS/s time domain Flash-SAR ADC

This paper presents a 10-bit subranging successive approximation register analog-to-digital converter (SAR ADC). A 3.5-bit time-domain coarse ADC converts the analog input to the time delay of two pulse signals and a time-to-digital converter (TDC) is used to quantize the delay. The coarse ADC controls the switching of the higher 3-bit capacitors in the digital-to-analog converter (DAC). A 7-bit SAR controls the remaining capacitors. The 1-bit redundancy corrects the linearity and mismatch error of the coarse ADC. The proposed 10-bit 100MS/s ADC is designed in a 65nm CMOS technology with 1.2V power supply. Simulation results show that this design achieves 59.7dB SNDR and consumes 2.69mW. The figure-of-merit (FoM) is 34.2fJ/conversion-step.

A low-jitter low-area PLL with process-independent bandwidth

The noise performance of PLL(Phase-Locked Loop) is closely related to the loop bandwidth. Unfortunately, process variation would influence ICP (charge pump current) and KVCO (gain of Voltage-Controlled-Oscillator), and then keep the PLL bandwidth sufficiently far away from the designed value. In this paper, a Digital Auxiliary Method (DAM) is proposed to reduce the change on ICP and KVCO due to process variation and stabilize the loop bandwidth. The PLL design is based on 0.18μm CMOS technology with a 1.8V power supply. Measurement results show that both of the variations are able to be compensated by the Digital Auxiliary Method and keep the bandwidth stable. Depending on the DAM, the output frequency of PLL is 200.68MHz which is 0.34% away from the designed value. The peak-to-peak jitter and rms jitter are 150.2ps and 30.6ps separately.

A CMOS dB-linear variable amplifier using curvematching

A CMOS dB-linear Variable Gain Amplifier (VGA) using Curvematching is presented. The CMOS dB-linear VGA provides a variable gain of 59dB while maintaining −3dB bandwidth greater than 86MHz. Curvematching is proposed to obtain the dB-linear gain control characteristics based on a low-distortion source-degenerated differential amplifier structure. Nonideal effects on dB linearity are analyzed and the methods for improvement are suggested. The VGA is designed in a 0.13μm CMOS technology and the post-simulation results demonstrate the good dB linearity, good property of total harmonic distortion and noise figure.

Design and realization of a voltage detector based on current comparison in a 40nm technology

A design of low-power voltage detector (VD) based on current comparison technology is presented. This VD samples the power supply voltage and converts the sampled voltage to a current which will be compared with a reference. The current comparison technology simplifies the design without use of the resistor string and voltage comparators, and thus reduces the core area. The VD detects three thresholds successively while keeping only one detecting portion working at a time to minimize power consumption. The VD is designed and realized in a standard 40nm process. The measurement result agrees well with designed parameters with 3s variations less than 100mV. Meanwhile, the power consumption keeps lower than 10μW.

An improved switched-emitter-follower for high-resolution GS/s-rate track-and-hold amplifiers

This paper presents an improved switched-emitter-follower for high-resolution GS/s-rate track-and-hold amplifier. A dummy switched-emitter-follower is introduced to compensate track-mode nonlinearity. And a clamping amplifier is utilized to reduce hold-mode feedthrough in high sample rate. The proposed switched-emitter-follower was chip verified in a 12bit 1GS/s THA based on 0.18pm SiGe BiCMOS process. Post-layout simulations show that the proposed THA achieves a spurious free dynamic range of 71 dB for 497 MHz input frequency at 1 GS/s rate. Operating from a 3.3V supply, the power dissipation of the proposed switched-emitter-follower is 156mW.

An inductive peaking technology for high-speed MIPI receiver bandwidth expanding in a 90 nm CMOS process

An inductive peaking technology is proposed in this paper for improving receiver bandwidth. A N/PMOS cross biasing active inductor and negative Miller capacitance are introduced to provide inductive peaking around the amplifier bandwidth. According to the simulation and experimental results within a MIPI receiver under 1.2V CMOS 90nm process, the inductive peaking technology increases the bandwidth of the preamplifier in the MIPI PHY circuit from 1.05GHz to 2.09GHz. As a results, the PHY circuit which employs the inductive peaking amplifier consumes only 4mW power for transferring 1Gbps data signal with 70mV differential amplitude to 1.2V CMOS level.

A transmitter with improved power efficiency realized by integrated transformer balun in 130nm Si technology

A low power radio-frequency transmitter with a transformer balun working at 2.4GHz is presented. The proposed transmitter is intended for use in a wide variety of low power medical and industrial portable wireless applications in the 2.4GHz ISM band. With the benefit of the transformer balun, the transmit power of the proposed transmitter increases 6dB while the power consumption remains the same. Designed in a 130nm CMOS technology, the proposed RF transmitter occupies 1.12mm2 and consumes 4.1mA from a 1.2V supply voltage. The transmit power is 0dBm.

A flash ADC based on VCO-based comparator with 26.3dB SFDR and 7.5M BW at 1V

This paper presents an architecture of flash analog to digital converters (ADCs) implemented with VCO-based comparators. The architecture reduce the power consumption of ADCs operating at high speed. The flash ADC is designed with 7 VCO-based compactors operating at 15MHz and simulated with CPPSIM. The signal to noise ratio (SNR), signal to noise and distortion ratio (SNDR), and spurious free dynamic range (SFDR) of the flash ADC are 17.5, 16.6 dB, and 26.3 dB, respectively with an input of 1MHz sine signal.

Design of a high resolution multi-phase clock generator based on DLL

This paper presents a multi-phase clock generator with high resolution based on DLL. By employing the static phase error, fine tuning step is achieved with the simplest DLL structure. The charging current and discharging current of charge pump (CP) are set to be unequal to get static phase error. The simulation results show the delay step resolution of the generator with 400MHz input is 5ps and the control voltage (VC) is 0.5V when DLL is locked.