Linqi Shi

PAM4 receiver with adaptive threshold voltage and adaptive decision feedback equalizer

A novel PAM4 receiver with adaptive threshold voltage, adaptive decision feedback equalizer and fixed linear equalizer has been presented. The proposed techniques enable threshold voltage to be adjusted automatically depending on data rate, signal swing and loss of channel. Consequently the receiver can be used in various situations without being manually calibrated. Adaptive decision feedback equalizer for PAM4 signaling is proposed, incorporated with sign-sign least mean square algorithm. Simulation results across lossy channel show proper convergence of threshold voltage and decision feedback equalizer values with the proposed receiver.

A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery

A 40 Gb/s PAM4 receiver with novel digital clock and data recovery (CDR) and one tap decision feedback equalizer (DFE) has been presented. Without sophisticated transition detection and selection modules, the proposed CDR utilizes three bang-bang phase detectors sampling all the transitions to detect the phase error between the data and clock, achieving larger transition density and CDR bandwidth. Eight interleaved 5 GHz clocks with sense amplifiers are utilized to sample the data and edge, decreasing the power consumption of DFE. Two serial sense amplifiers are used to improve the gain, while two sets of phase interpolators are implemented to reduce the delay of the DFE loop. The 40 Gb/s PAM4 receiver is realized in 65nm CMOS technology. It provides as much as 16.7 dB equalization with linear equalizer and DFE. The overall power consumption is 74.9 mW at 1.2V supply, achieving a power efficiency of 1.87pJ/bit.

A speculative clock and data recovery architecture for multi-gigabit/s series links

This paper presents a speculative architecture of a digital phase-locked loop (DPLL)-based clock and data recovery (CDR) for high-speed receiver in series links. This proposed system removes pipeline stages and reduces propagation delays, as a result, the latency of the loop decreases, which improves the loop stability and jitter tolerance without sacrificing loop bandwidth. This system can realize locking the phase to 1/32 UI and the frequency to 30.51 ppm/lsb, with maximum frequency offset of +/- 6836 ppm.

A 6.5-GHz digitally-controlled oscillatorwith supply sensitivity of 0.0071%-f DCO /1%-V DD

This paper presents a 65nm CMOS 6.5GHz digitally-controlled oscillator (DCO) with static and dynamic supply sensitivity of 0.00138%-fDCO/1%-VDD and 0.0071%-fDCO/1%-VDD respectively. By regulating the supply current of DCO, the proposed technique achieves high supply-noise rejection performance. In addition, the proposed DCO has a strong immunity against process and achieves satisfied performance at different corners. The proposed DCO system achieves a phase noise of -107.4dBc/Hz @1MHz and -130.1dBc/Hz @10MHz offset from the carrier and operates from 6.3 GHz to 6.8 GHz, while consuming 3.2mW from a 1.2V supply at 6.5 GHz.

A 10GHz analogphase interpolator based on a novel quadrature clock generator

A 10GHz analog phase interpolator (PI) in Global Foundry 65nm CMOS technology has been presented. The PI mainly consists of the quadrature clock generator (QCG) and the phase Mixer. Different from the traditional divider, the QCG produces 4-phase clocks without reducing the clock frequency. As a result, it reduces the frequency of PLL from 20GHz to 10GHz, which can largely save the power consumption of the clocking system. Compared with the traditional QCG, the proposed QCG achieves a lower output phase error and has a better tolerance of delay variation. With the delay changing from 18ps to 36ps, the output phase error of the proposed QCG keeps within ±4°. Besides, the simulated worst phase step error of the phase Mixer is smaller than 0.2LSB. The whole phase interpolator has the worst phase step error smaller than 0.3LSB. The average power consumption of the QCG and the phase Mixer are 6.14mW and 4.14mW respectively, with a 1.2V supply voltage.