Weixin Gai

A novel frequency search algorithm to achieve fast locking without phase tracking in ADPLL

A novel frequency search algorithm is proposed in this paper to achieve fast locking in all digital PLL (ADPLL) with no phase tracking being required. According to phase and frequency error, the normalized tuning word (NTW) is calculated so that the output frequency reaches the desired frequency immediately. As the non-idealities, such as DCO gain estimation error and TDC finite resolution, greatly affect the accuracy of the calculation, the output frequency is continuously measured and frequency error is averaged to minimize those impacts. With 0.13um CMOS process, the proposed ADPLL operates at 2.7 GHz and achieves 0.35 us locking time while consuming 7.47mW.

A 2-tap 40-Gb/s 4-PAM transmitter with level selection based pre-emphasis

This paper presents a 2-tap 40-Gb/s 4-PAM transmitter with level selection based pre-emphasis. The parallel input to the transmitter is pre-coded at low frequencies, so that the pre-emphasis tap injects different currents into the output node of the transmitter based on different level changes of the output signal. The proposed pre-emphasis suppresses overshooting and lowers power consumption. The test chip is fabricated in a SMIC 65-nm CMOS process and shows a 45.2 mW power dissipation while operating at 20-GS/s, which is equivalent to 40-Gb/s.

PAM4 receiver with adaptive threshold voltage and adaptive decision feedback equalizer

A novel PAM4 receiver with adaptive threshold voltage, adaptive decision feedback equalizer and fixed linear equalizer has been presented. The proposed techniques enable threshold voltage to be adjusted automatically depending on data rate, signal swing and loss of channel. Consequently the receiver can be used in various situations without being manually calibrated. Adaptive decision feedback equalizer for PAM4 signaling is proposed, incorporated with sign-sign least mean square algorithm. Simulation results across lossy channel show proper convergence of threshold voltage and decision feedback equalizer values with the proposed receiver.

A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery

A 40 Gb/s PAM4 receiver with novel digital clock and data recovery (CDR) and one tap decision feedback equalizer (DFE) has been presented. Without sophisticated transition detection and selection modules, the proposed CDR utilizes three bang-bang phase detectors sampling all the transitions to detect the phase error between the data and clock, achieving larger transition density and CDR bandwidth. Eight interleaved 5 GHz clocks with sense amplifiers are utilized to sample the data and edge, decreasing the power consumption of DFE. Two serial sense amplifiers are used to improve the gain, while two sets of phase interpolators are implemented to reduce the delay of the DFE loop. The 40 Gb/s PAM4 receiver is realized in 65nm CMOS technology. It provides as much as 16.7 dB equalization with linear equalizer and DFE. The overall power consumption is 74.9 mW at 1.2V supply, achieving a power efficiency of 1.87pJ/bit.

A 1.27mW 20Gbps 1:16 DEMUX with a symmetrical-edge-delay sense amplifier

A high-speed low-power 1:16 demultiplexer with a novel symmetrical-edge-delay sense amplifier is presented in this paper. The traditional Sense-Amplifier-Based Flip-Flop (SAFF) has asymmetric rising and falling edges with the fact that the falling edge lags the rising edge the time of a gate delay, which has become a bottleneck of speed. In order to overcome the problem of nonsymmetry of output data edges caused by the set-reset (SR) latch in the Sense-Amplifier-Based Flip-Flop, a new slave latch controlled by the clock is proposed which reduces delay and improves sensitivity considerably. A new type of CMOS logic 2:16 DEMUX is also proposed which can save about 20% area and 15% power consumption compared with the conventional structure. The power consumption of DEMUX is only 0.36mW at the date rate of 10Gb/s and 1.27mW at 20Gb/s. The proposed structure is based on Global Foundry 65nm CMOS process.

A speculative clock and data recovery architecture for multi-gigabit/s series links

This paper presents a speculative architecture of a digital phase-locked loop (DPLL)-based clock and data recovery (CDR) for high-speed receiver in series links. This proposed system removes pipeline stages and reduces propagation delays, as a result, the latency of the loop decreases, which improves the loop stability and jitter tolerance without sacrificing loop bandwidth. This system can realize locking the phase to 1/32 UI and the frequency to 30.51 ppm/lsb, with maximum frequency offset of +/- 6836 ppm.

A 6.5-GHz digitally-controlled oscillatorwith supply sensitivity of 0.0071%-f DCO /1%-V DD

This paper presents a 65nm CMOS 6.5GHz digitally-controlled oscillator (DCO) with static and dynamic supply sensitivity of 0.00138%-fDCO/1%-VDD and 0.0071%-fDCO/1%-VDD respectively. By regulating the supply current of DCO, the proposed technique achieves high supply-noise rejection performance. In addition, the proposed DCO has a strong immunity against process and achieves satisfied performance at different corners. The proposed DCO system achieves a phase noise of -107.4dBc/Hz @1MHz and -130.1dBc/Hz @10MHz offset from the carrier and operates from 6.3 GHz to 6.8 GHz, while consuming 3.2mW from a 1.2V supply at 6.5 GHz.

A 10GHz analogphase interpolator based on a novel quadrature clock generator

A 10GHz analog phase interpolator (PI) in Global Foundry 65nm CMOS technology has been presented. The PI mainly consists of the quadrature clock generator (QCG) and the phase Mixer. Different from the traditional divider, the QCG produces 4-phase clocks without reducing the clock frequency. As a result, it reduces the frequency of PLL from 20GHz to 10GHz, which can largely save the power consumption of the clocking system. Compared with the traditional QCG, the proposed QCG achieves a lower output phase error and has a better tolerance of delay variation. With the delay changing from 18ps to 36ps, the output phase error of the proposed QCG keeps within ±4°. Besides, the simulated worst phase step error of the phase Mixer is smaller than 0.2LSB. The whole phase interpolator has the worst phase step error smaller than 0.3LSB. The average power consumption of the QCG and the phase Mixer are 6.14mW and 4.14mW respectively, with a 1.2V supply voltage.

A novel 6-Gbps half-rate SST transmitter with impedance calibration and adjustable pre-emphasis

A novel half-rate source-series-terminated (SST) transmitter in 65nm bulk CMOS technology is presented in this paper. Compared to previous half-rate SST transmitters, the proposed one consists of four binary-weighted slices increasing proportionally as 1x, 2x, 4x and 8x and the range of pre-emphasis level is increased greatly by the clock-match block to adapt to different channel. The half-rate transmitter can adjust the pre-emphasis level from 1.2dB to 23dB. The transmitter output impedance is adjustable from 33ohms to 64ohms. A power consumption of 24mW is measured at a transmit rate of 6 GB/s which is power-efficient compared to previous half-rate SST transmitter.

A novel 40-Gb/S PAM4 transmitter with power-efficient pre-emphasis

This paper presents a 65-nm CMOS 40-Gb/s PAM4 transmitter with power-efficient pre-emphasis. Switchable current sources are used in the pre-emphasis tap to eliminate power wasting. The pre-emphasis tap only injects current to the output nodes upon the voltage level transition of the output signal. Current does not flow through the pre-emphasis tap when there is no transition. Simulation results show that with insertion loss of the channel being 20.2 dB at 20 GHz, an eye height of 120 mV and an eye width of 30 ps are achieved. The driver consumes only 18.3 mW, which is equivalent to 0.46-pJ/b.