Linus Fröberg

Vertical high-mobility wrap-gated InAs nanowire transistor

In this letter, the authors demonstrate a vertical wrap-gated field-effect transistor based on InAs nanowires [Proc. DRC, 2005, p. 157]. The nanowires have a diameter of 80 nm and are grown using selective epitaxy; a matrix of typically 10 /spl times/ 10 vertically standing wires is used as channel in the transistor. The authors measure current saturation at V/sub ds/=0.15 V (V/sub g/=0 V), and a high mobility, compared to the previous nanowire transistors, is deduced.

Strain mapping in free-standing heterostructured wurtzite InAs/InP nanowires

The strain distribution in heterostructured wurtzite InAs/InP nanowires is measured by a peak finding technique using high resolution transmission electron microscopy images. We find that nanowires with a diameter of about 20 nm show a 10 nm strained area over the InAs/InP interface and the rest of the wire has a relaxed lattice structure. The lattice parameters and elastic properties for the wurtzite structure of InAs and InP are calculated and a nanowire interface is simulated using finite element calculations. Both the method and the experimental results are validated using a combination of finite element calculations and image simulations.

Development of a Vertical Wrap-Gated InAs FET

In this paper, we report on the development of a vertical wrap-gated field-effect transistor based on epitaxially grown InAs nanowires. We discuss some of the important steps involved in the growth and processing, such as nanowire position control, in situ doping, high- kappa dielectric deposition, spacer layer formation, and metal wrap-gate fabrication. In particular, we compare a few alternative methods for deposition of materials onto vertical structures and discuss their potential advantages and limitations. Finally, we also present a comparison of transistor performance for nanowires grown using two different epitaxial techniques.

Tunable effective g factor in InAs nanowire quantum dots

We report tunneling spectroscopy measurements of the Zeeman spin splitting in InAs few-electron quantum dots. The dots are formed between two InP barriers in InAs nanowires with a wurtzite crystal structure grown using chemical beam epitaxy. The values of the electron g factors of the first few electrons entering the dot are found to strongly depend on dot size. They range from close to the InAs bulk value in large dots vertical bar g(*)vertical bar=13 down to vertical bar g(*)vertical bar=2.3 for the smallest dots.

The electrical and structural properties of n-type InAs nanowires grown from metal–organic precursors

The electrical and structural properties of 111B-oriented InAs nanowires grown using metal-organic precursors have been studied. On the basis of electrical measurements it was found that the trends in carbon incorporation are similar to those observed in the layer growth, where an increased As/In precursor ratio and growth temperature result in a decrease in carbon-related impurities. Our results also show that the effect of non-intentional carbon doping is weaker in InAs nanowires compared to bulk, which may be explained by lower carbon incorporation in the nanowire core. We determine that differences in crystal quality, here quantified as the stacking fault density, are not the primary cause for variations in resistivity of the material studied. The effects of some n-dopant precursors (S, Se, Si, Sn) on InAs nanowire morphology, crystal structure and resistivity were also investigated. All precursors result in n-doped nanowires, but high precursor flows of Si and Sn also lead to enhanced radial overgrowth. Use of the Se precursor increases the stacking fault density in wurtzite nanowires, ultimately at high flows leading to a zinc blende crystal structure with strong overgrowth and very low resistivity.

Surface diffusion effects on growth of nanowires by chemical beam epitaxy

Surface processes play a large role in the growth of semiconductor nanowires by chemical beam epitaxy. In particular, for III-V nanowires the surface diffusion of group-III species is important to understand in order to control the nanowire growth. In this paper, we have grown InAs-based nanowires positioned by electron beam lithography and have investigated the dependence of the diffusion of In species on temperature, group-III and -V source pressure and group-V source combinations by measuring nanowire growth rate for different nanowire spacings. We present a model which relates the nanowire growth rate to the migration length of In species. The model is fitted to the experimental data for different growth conditions, using the migration length as fitting parameter. The results show that the migration length increases with decreasing temperature and increasing group-V/group-III source pressure ratio. This will most often lead to an increase in growth rate, but deviations will occur due to incomplete decomposition and changes in sticking coefficient for group-III species. The results also show that the introduction of phosphorous precursor for growth of InAs1−xPx nanowires decreases the migration length of the In species followed by a decrease in nanowire growth rate. (Less)

Electrical properties of self-assembled branched InAs nanowire junctions

We investigate electrical properties of self-assembled branched InAs nanowires. The branched nanowires are catalytically grown using chemical beam epitaxy, and three-terminal nanoelectronic devices are fabricated from the branched nanowires using electron-beam lithography. We demonstrate that, in difference from conventional macroscopic junctions, the fabricated self-assembled nanowire junction devices exhibit tunable nonlinear electrical characteristics and a signature of ballistic electron transport. As an example of applications, we demonstrate that the self-assembled three-terminal nanowire junctions can be used to implement the functions of frequency mixing, multiplication, and phase-difference detection of input electrical signals at room temperature. Our results suggest a wide range of potential applications of branched semiconductor nanostructures in nanoelectronics.

Transients in the Formation of Nanowire Heterostructures

We present results on the effect of seed particle reconfiguration on the growth of short InAs and InP nanowire segments. The reconfiguration originates in two different steady state alloy compositions of the Au/In seed particle during growth of InAs and InP. From compositional analysis of the seed particle, the In content in the seed particle is determined to be 34 and 44% during InAs and InP growth, respectively. When switching between growing InAs and InP, transient effects dominate during the time period of seed particle reconfiguration. We developed a model that quantitatively explains the effect and with the added understanding we are now able to grow short period (<10 nm) nanowire superlattices.

Direct Atomic Scale Imaging of III-V Nanowire Surfaces.

We have succeeded in direct atomic scale imaging of the exterior surfaces of III-V nanowires by scanning tunneling microscopy (STM). By using atomic hydrogen, we expose the crystalline surfaces of InAs nanowires with regular InP segments in vacuum while retaining the wire morphology. We show images with atomic resolution of the two major types of InAs wurtzite nanowire surface facets and scanning tunneling spectroscopy (STS) data. Ab initio calculations of the lowest energy surface structures and simulated STM images, agree very well with experiments.

Nanowire-based multiple quantum dot memory

The authors propose and demonstrate an alternative memory concept in which a storage island is connected to a nanowire containing a stack of nine InAs quantum dots, each separated by thin InP tunnel barriers. Transport through the quantum dot structure is suppressed for a particular biasing window due to misalignment of the energy levels. This leads to hysteresis in the charging/discharging of the storage island. The memory operates for temperatures up to around 150 K and has write times down to at least 15 ns. A comparison is made to a nanowire memory based on a single, thick InP barrier.