Linxiao Zhang

Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays

Over the past decade, we have witnessed the maturation of silicon-based phased array technology, which has started to make an impact on commercial and military wireless applications. Over the next decade, driven by the development of next-generation wireless communication networks, we will see the maturation and impact of large-scale multiple-input-multiple-output (MIMO) technology. MIMO receiver arrays exploit digital array signal processing, and consequently are exposed to interference in the analog and radio-frequency (RF) front ends. The absence of analog/RF interference mitigation in traditional digital MIMO receiver arrays results in designs with high-dynamic-range and power-hungry analog and RF receiver front ends and analog-to-digital converters. This paper describes recently developed techniques for spatio-spectral interference mitigation in the analog and RF domain for digital MIMO receivers. The techniques proposed are flexible; tunable across operating frequency; scalable; present low cost, size, and power consumption overheads; and are experimentally validated through a 0.1-1.7-GHz four-element receiver front-end array integrated circuit (IC) prototype in 65-nm complementary metal-oxide-semiconductor (CMOS) technology.

9.2 A scalable 0.1-to-1.7GHz spatio-spectral-filtering 4-element MIMO receiver array with spatial notch suppression enabling digital beamforming

Multiple-antenna receivers offer numerous advantages over single-antenna receivers, including sensitivity improvement, ability to reject interferers spatially and enhancement of data-rate or link reliability via MIMO. In the recent past, RF/analog phased-array receivers have been investigated [1-4]. On the other hand, digital beamforming offers far greater flexibility, including ability to form multiple simultaneous beams, ease of digital array calibration and support for MIMO. However, ADC dynamic range is challenged due to the absence of spatial interference rejection at RF/analog.

Scalable Spatial Notch Suppression in Spatio-Spectral-Filtering MIMO Receiver Arrays for Digital Beamforming

Large-scale multiple-input-multiple-output(MIMO) technology is drawing significant interest for the next-generation wireless networks. Traditional MIMO receiver architectures use multiple parallel receiver front ends with digitization at every element to support digital space-time array processing. The absence of analog/RF spatial interference mitigation in traditional digital MIMO receiver arrays results in a high dynamic-range requirement, and consequently, power-hungry analog and RF receiver front ends and analog-to-digital converters. This paper presents a scalable 65 nm CMOS 0.1-1.7 GHz spatio-spectral-filtering four-element MIMO receiver array with spatial notch suppression that protects the analog/RF circuits and analog-to-digital converters from spatial interference early in the signal chain. The combination of spatial and spectral filtering results in more than 19 dB rejection irrespective of the frequency at which the spatial blocker is located. The proposed spatial notch suppression technique improves the measured in-band OIP3 from -10 to +24 dBV, and the measured out-of-band IIP3 from +11 to +18 dBm. Furthermore, turning on the spatial notch suppression leads to minimal noise figure degradation. The proposed chip architecture is scalable on board without the need for RF interconnections. A wireless imaging demo shows two of the implemented integrated circuits tiled on board to form an eight-element MIMO receiver array that is able to detect a weak desired signal in the presence of an in-band 15 dB stronger spatial blocker.

24.2 A 0.1-to-3.1GHz 4-element MIMO receiver array supporting analog/RF arbitrary spatial filtering

Digital receiver (RX) arrays featuring ADCs at each element enable massive multi-in-multi-out (MIMO) applications, but since spatial interference rejection is absent in the RF/analog domain, RF/analog/ADC dynamic range is challenged in an environment where strong and weak spatially distinct in-band signals co-exist. Recent MIMO RX array works [1,2] attempt to mitigate this problem with (single) spatial notch suppression in the RF/analog domain, while still maintaining multiple outputs to support MIMO. However, multiple spatial interference signals at different power levels can be present, and reflections and scattering can make the power distribution in the spatial domain more hostile. A single spatial notch is insufficient in such realistic scenarios. Secondly, the notch suppression bandwidth (BW) is typically limited, as is the case with conventional cancellation architectures. Thirdly, reconfigurable wideband MIMO RX arrays that rely on impedance translation concepts in RF switched-capacitor circuits seldom operate effectively beyond 2GHz in CMOS [1].

RF channelizer architectures using Iterative Downconversion for concurrent or fast-switching spectrum analysis

We propose an RF channelizer architecture that uses the concept of 3-way Iterative Down-Conversion (IDC) to channelize a wideband incident spectrum while only using a fixed LO synthesizer. The proposed architecture can realize a concurrent channelizer that can analyze channels simultaneously, or a fast-switching channelizer that can analyze channels sequentially but with very short switching times between channels. We present an RF channelizer demonstrator prototype that was fabricated in a 65nm CMOS process. It implements a partially-concurrent architecture with the ability to concurrently down-convert a subset of channels while being able to switch very quickly between the non-concurrent channels. It splits an input spectrum of 0.6GHz-9GHz into 7 channels each of 1.2GHz bandwidth. Channelizer performance depends on the selected operation mode. The measured channel switching duration can be as fast as 8ns, and is always under 1μs. The chip occupies an area of 2mm × 1mm and consumes an average power of 435mW while offering a dynamic range between 58dB to 63dB based on noise and linearity performance.

Analysis and Design of a 0.6- to 10.5-GHz LNTA for Wideband Receivers

A low-noise transconductance amplifier (LNTA) for wideband receivers based on a gm-boosted current mirroring topology that operates over 0.6- to 10.5-GHz is presented. gm boosting relaxes the Gm and S11 bandwidth (BW) tradeoff and the noise figure (NF) and input matching tradeoff. The active feedback synthesizes a second-order input impedance profile that further extends the S11 BW. Despite the high Gm obtained over large BW, high linearity is maintained through the predistortion inherent in the current mirroring topology. The LNTA is used in a 65-nm CMOS wideband channelizing iterative downconversion receiver targeting spectrum and signal analysis for cognitive radio and performs active signal splitting across two paths with a total postlayout simulated Gm of 242 mS (170 and 72 mS in paths 1 and 2, respectively). S11 BW and Gm BW both exceed 10.5 GHz. Minimum LNTA NFs simulated in the two paths are 4 and 4.8 dB, respectively. Simulated wideband IIP3 and blocker P1dB are +6 and +1.5 dBm, respectively. Measurements of a direct conversion receiver in path 2 closely match simulations.

Recent advances in analog/RF interference mitigation for massive MIMO receivers

Digital MIMO receivers featuring digitization at each element are critical for (massive) MIMO applications since they support complex space-time signal processing. However, the lack of spatial selectivity in the analog/RF domain necessitates high-dynamic-range analog-to-digital converters (A/Ds) to accommodate the uneven spatial power distribution, limiting the scale of such MIMO systems. This paper reviews analog/RF spatial filtering techniques that have been proposed in recent years to address this problem. A scalable spatial notch suppression technique allows the synthesis of a steerable spatial notch, which eliminates the strongest in-band spatial block in the analog/RF domain. The spatial notch is synthesized in the baseband, and the impedance transparency of passive mixers is used to translate the notch to the antenna interface. In a second prototype, a more general arbitrary spatial filter (ASF) adaptively filters the spatial domain signals to equalize the power levels across all directions. Current mode operation ensures superior linearity and ultra-wideband spatial suppression. Measurements from CMOS prototypes have been provided to verify the claims.

Linear Periodically Time-Varying (LPTV) Circuits Enable New Radio Architectures for Emerging Wireless Communication Paradigms: Extended Abstract: Invited

The next generation of cellular wireless communication networks (the much hyped “5G”) is targeting a 1000x increase in data capacity. This has sparked an investigation of new and transformative wireless communication paradigms, including massive MIMO, full duplex and millimeter-wave wireless. These new wireless paradigms place requirements on the radio circuitry that are orders of magnitude more challenging than traditional systems, forcing us to rethink conventional radio design. Conventional analog and radio frequency circuit design has relied on linear, time-invariant (LTI) components and circuits. However, LTI components and circuits are restricted in the signal processing functionalities that can be implemented. Recently, there has been significant interest in linear, periodically time varying (LPTV) circuits that can enable new functionalities and components, such as highly-tunable, high quality integrated filters, front-ends with spatio-spectral filtering capability and integrated non-magnetic non-reciprocal components such as circulators and isolators. This paper reviews recent research breakthroughs in LPTV circuits and systems that enable full-duplex and massive MIMO wireless.