Harish Krishnaswamy

Silicon-Based Ultra-Wideband Beam-Forming

Ultra-wideband (UWB) beam-forming, a special class of multiple-antenna systems, allows for high azimuth and depth resolutions in ranging and imaging applications. This paper reports a fully integrated UWB beam-former featuring controllable true time delay and power gain. Several system and circuit level parameters and characterization methods influencing the design and testing of UWB beam-formers are discussed. A UWB beam-former prototype for imaging applications has been fabricated with the potential to yield 20 mm of range resolution and a 7deg angular resolution from a four-element array with 10 mm element spacing. The UWB beam-former accomplishes a 4-bit delay variation for a total of 64 ps of achievable group delay with a 4-ps resolution, a 5-dB gain variation in 1-dB steps, and a worst case -3-dB gain bandwidth of 13 GHz. Overall operation is achieved by the integration of a 3-bit tapped delay trombone-type structure with a 4-ps variable delay resolution, a 1-bit, 32-ps fixed delay coplanar-type structure, and a variable-gain distributed amplifier. The prototype chip fabricated in a 0.18 mum BiCMOS SiGe process occupies 1.6 mm2 of silicon area and consumes 87.5 mW from a 2.5-V supply at the maximum gain setting of 10 dB

Magnetic-free non-reciprocity based on staggered commutation

Lorentz reciprocity is a fundamental characteristic of the vast majority of electronic and photonic structures. However, non-reciprocal components such as isolators, circulators and gyrators enable new applications ranging from radio frequencies to optical frequencies, including full-duplex wireless communication and on-chip all-optical information processing. Such components today dominantly rely on the phenomenon of Faraday rotation in magneto-optic materials. However, they are typically bulky, expensive and not suitable for insertion in a conventional integrated circuit. Here we demonstrate magnetic-free linear passive non-reciprocity based on the concept of staggered commutation. Commutation is a form of parametric modulation with very high modulation ratio. We observe that staggered commutation enables time-reversal symmetry breaking within very small dimensions (λ/1,250 × λ/1,250 in our device), resulting in a miniature radio-frequency circulator that exhibits reduced implementation complexity, very low loss, strong non-reciprocity, significantly enhanced linearity and real-time reconfigurability, and is integrated in a conventional complementary metal–oxide–semiconductor integrated circuit for the first time.

High power, high efficiency stacked mmWave Class-E-like power amplifiers in 45nm SOI CMOS

Stacking devices in CMOS power amplifiers (PAs) increases the achievable output voltage swing, thereby increasing the output power and efficiency, particularly at millimeter-wave frequencies. This work presents stacked CMOS PAs based on an improved Class-E design methodology, where device loss is explicitly accounted for in the analysis and design procedure. Design guidelines and fundamental limits on achievable performance are presented. Two fully-integrated 45GHz prototypes with 2 and 4 stacked devices have been fabricated in IBMs 45nm SOI CMOS technology. Measurement results yield a peak PAE of 34.6% for the 2-stacked PA with a saturated output power of 17.6 dBm, and a peak PAE of 19.4% for the 4-stacked PA with a saturated output power of 20.3 dBm. The former represents the highest PAE reported for CMOS mmWave PAs, and the latter represents the highest output power achieved from a CMOS mmWave PA. The paper also describes the modeling of active and passive devices for mmWave CMOS PAs for good model-hardware correlation.

Integrated Wideband Self-Interference Cancellation in the RF Domain for FDD and Full-Duplex Wireless

A fully integrated technique for wideband cancellation of transmitter (TX) self-interference (SI) in the RF domain is proposed for multiband frequency-division duplexing (FDD) and full-duplex (FD) wireless applications. Integrated wideband SI cancellation (SIC) in the RF domain is accomplished through: 1) a bank of tunable, reconfigurable second-order high-Q RF bandpass filters in the canceller that emulate the antenna interfaces isolation (essentially frequency-domain equalization in the RF domain) and 2) a linear N-path Gm-C filter implementation with embedded variable attenuation and phase shifting. A 0.8-1.4 GHz receiver (RX) with the proposed wideband SIC circuits is implemented in a 65 nm CMOS process. In measurement, >20 MHz 20 dB cancellation bandwidth (BW) is achieved across frequency-selective antenna interfaces: 1) a custom-designed LTElike 0.780/0.895 GHz duplexer with TX/RX isolation peak magnitude of 30 dB, peak group delay of 11 ns, and 7 dB magnitude variation across the TX band for FDD and 2) a 1.4 GHz antenna pair for FD wireless with TX/RX isolation peak magnitude of 32 dB, peak group delay of 9 ns, and 3 dB magnitude variation over 1.36-1.38 GHz. For FDD, SIC enhances the effective outof-band (OOB) IIP3 and IIP2 to +25-27 dBm and +90 dBm, respectively (enhancements of 8-10 and 29 dB, respectively). For FD, SIC eliminates RX gain compression for as high as -8 dBm of peak in-band (IB) SI, and enhances effective IB IIP3 and IIP2 by 22 and 58 dB.

Low-Noise Active Cancellation of Transmitter Leakage and Transmitter Noise in Broadband Wireless Receivers for FDD/Co-Existence

A technique for active cancellation of transmitter self-interference in wideband receivers is presented. The active TX leakage cancellation circuitry is embedded within a noise-cancelling low-noise transconductance amplifier (LNTA) so that the noise and the distortion of the cancellation circuitry are cancelled, resulting in a noise-cancelling, self-interference cancelling receiver (NC-SIC RX). A second-point cancellation of TX noise in the RX band is performed after the LNTA so that the noise impact of the second canceller is reduced. Theoretical analyses related to the benefits and limits of active self-interference cancellation as well as the simultaneous cancellation of the noise and distortion of the cancellation circuitry are presented. A 0.3-1.7 GHz receiver with the proposed active cancellation is implemented in 65 nm CMOS. The proposed scheme can cancel up to +2 dBm peak TX leakage at the receiver input. The triple beat at +2 dBm peak TX leakage is 68 dB and the effective IIP3 is +33 dBm, representing increases of 38 and 19 dB, respectively, over the receiver without cancellation. The associated increase in receiver NF is less than 0.8 dB. In addition, the scheme effectively suppresses TX noise in RX band by up to 13 dB. The technique can be more generally viewed as an active combining structure that has ideally no noise penalty and is able to handle large signals without generating distortion and can be applied to any scenario where a replica of an interference signal can be generated.

High-Power High-Efficiency Class-E-Like Stacked mmWave PAs in SOI and Bulk CMOS: Theory and Implementation

Series stacking of multiple devices is a promising technique that can help overcome some of the fundamental limitations of CMOS technology in order to improve the output power and efficiency of CMOS power amplifiers (PAs), particularly at millimeter-wave (mmWave) frequencies. This paper investigates the concept of device stacking in the context of the Class-E family of nonlinear switching PAs at mmWave frequencies. Fundamental limits on achievable performance of a stacked configuration are presented along with design guidelines for a practical implementation. In order to demonstrate the utility of stacking, three prototypes have been implemented: two fully integrated 45-GHz single-ended Class-E-like PAs with two- and four-stacked devices in IBMs 45-nm silicon-on-insulator (SOI) CMOS technology, and a 45-GHz differential Class-E-like PA with two devices stacked in IBMs 65-nm low-power CMOS process. Measurement results yield a peak power-added efficiency (PAE) of 34.6% for the two-stacked 45-nm SOI CMOS PA with a saturated output power of 17.6 dBm. The measurement results also indicate true Class-E-like switching PA behavior. A peak PAE of 19.4% is measured for the four-stacked PA with a saturated output power of 20.3 dBm. The two-stacked PA exhibits the highest PAE reported for CMOS mmWave PAs, and the four-stacked PA achieves the highest output power from a fully integrated CMOS mmWave PA including those that employ power combining. The 65-nm CMOS differential two-stacked PA exhibits a peak PAE of 28.3% with a saturated differential output power of 18.2 dBm, despite the poor ON-resistance of the 65-nm low-power nMOS devices. This paper also describes the modeling of active devices for mmWave CMOS PAs for good model-hardware correlation.

A Fully Integrated 24GHz 4-Channel Phased-Array Transceiver in 0.13μm CMOS Based on a Variable-Phase Ring Oscillator and PLL Architecture

A fully integrated 24GHz 4-channel phased-array transceiver in 0.13μm CMOS is reported. The architecture is based on a variable-phase ring oscillator in a PLL that modulates the baseband for each antenna in the TX mode and downconverts the received signal from all antennas in the RX mode without using RF mixers, signal-path phase shifters, or any power combining network. The 2.3 × 2.1 mm2 chip achieves an array transmit EIRP > 23.8dBm, RX gain > 42dB, and can scan the beam continuously

216- and 316-GHz 45-nm SOI CMOS Signal Sources Based on a Maximum-Gain Ring Oscillator Topology

This paper introduces a maximum-gain ring oscillator (MGRO) topology that maximizes the power gain (PG) achieved by the active devices in a ring oscillator using appropriately designed passive matching networks to maximize the frequency of oscillation. A design methodology is provided along with expressions for the passive matching elements. In the absence of passive losses, the topology can oscillate at the fmax of the active devices. In the presence of passive loss, for the first time, the losses can be taken into account in a closed-form fashion to maximize device PG, and consequently, oscillation frequency. Based on this topology, two different oscillators operating at approximately 108 and 158 GHz are implemented using the 56-nm body-contacted devices (fmax ≈ 200 GHz) of IBMs 45-nm silicon-on-insulator CMOS technology. The fact that these two oscillators function well with marginal startup gains of 2.62 and 0.62 dB, respectively, demonstrates the robustness of the techniques described here. The second harmonic of the oscillation is extracted using a load-pull-optimized extraction network. This topology can be generalized for the extraction of any harmonic from MGROs with a different number of stages. The oscillators generate -14.4 dBm at 216.2 GHz and -21 dBm at 316.5 GHz while drawing 57.5 and 46.4 mW of dc power, respectively. This paper also describes the modeling of CMOS active and passive devices for high millimeter-wave and sub-millimeter-wave integrated-circuit design.

9.8 Receiver with integrated magnetic-free N-path-filter-based non-reciprocal circulator and baseband self-interference cancellation for full-duplex wireless

Full-duplex (FD) is an emergent wireless communication paradigm where the transmitter (TX) and the receiver (RX) operate at the same time and at the same frequency. The fundamental challenge with FD is the tremendous amount of TX self-interference (SI) at the RX. Low-power applications relax FD system requirements [1], but an FD system with -6dBm transmit power, 10MHz signal bandwidth and 12dB NF budget still requires 86dB of SI suppression to reach the -92dBm noise floor. Recent research has focused on techniques for integrated self-interference cancellation (SIC) in FD receivers [1-3]. Open challenges include achieving the challenging levels of SIC through multi-domain cancellation, and low-loss shared-antenna (ANT) interfaces with high TX-to-RX isolation. Sharedantenna interfaces enable compact form factor, translate easily to MIMO, and ease system design through channel reciprocity.

Calibration-Kit Design for Millimeter-Wave Silicon Integrated Circuits

We study and present design guidelines for thru-reflect-line vector-network-analyzer calibration kits used for characterizing circuits and transistors fabricated on silicon integrated circuits at millimeter-wave frequencies. We compare contact-pad designs and develop fixed-fill contacts that achieve both repeatable and low contact-pad capacitances. We develop a fill-free and mesh-free transmission line structure for the calibration kit and compare it to similar transmission lines with meshed ground plane. We also develop a gold plating process that greatly improves contact repeatability, permitting the use of redundant multiline calibrations. This in turn simplifies the development of an error analysis. Finally, we apply the technique to state-of-the-art transistor characterization, and present measured results with uncertainties.