Liqiong Wei

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks

Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been verified by IISPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.

Design and optimization of dual-threshold circuits for low-voltage low-power applications

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

Design and optimization of low voltage high performance dual threshold CMOS circuits

Reduction in leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been verified by IISPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50%.

High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness

Power optimization has become an important issue for high performance designs. One way to achieve low-power and high performance circuits is to use dual-threshold voltages. High threshold transistors can be used in non-critical paths to reduce the leakage power, while lower threshold voltage is used for transistors in critical path(s) to achieve high performance. This paper proposes two low power and high performance CMOS design techniques-multiple channel length (M/sub L/CMOS) and multiple oxide thickness (M/sub ox/CMOS), based on dual V/sub th/, design technique. A comprehensive algorithm for selecting and assigning optimal transistor threshold voltage, channel length and oxide thickness is given. The simulation results on ISCAS benchmark circuits show that the total power consumption can be reduced by 21% for M/sub L/CMOS at low activity. Total power savings for M/sub ox/CMOS at low and high switching activities are about 42% and 24%, respectively.

Mixed-V/sub th/ (MVT) CMOS circuit design methodology for low power applications

Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical paths, while a low-threshold is used in critical path(s) to maintain the performance. Mixed-V/sub th/ (MVT) static CMOS design technique allows different thresholds within a logic gate, thereby increasing the number of high threshold transistors compared to the gate-level dual threshold technique. In this paper, a methodology for MVT CMOS circuit design is presented. Different MVT CMOS circuit schemes are considered and three algorithms are proposed for the transistor-level threshold assignment under performance constraints. Results indicate that MVT CMOS design technique can provide about 20% more leakage reduction compared to the corresponding gate-level dual threshold technique.

Low voltage low power CMOS design techniques for deep submicron ICs

Due to the quadratic reduction in the switching power dissipation, lowering supply voltage is obviously one of the most effective ways to reduce power consumption. However, the performance will degrade. In order to satisfy the high performance requirements, threshold voltage has to be scaled. Unfortunately, such scaling leads to a dramatic increase in leakage current, which becomes a new concern for low voltage and high performance circuit designs. Multiple transistor threshold and supply voltages can be used to achieve low power and high performance while maintaining low leakage current. In this tutorial, different multiple-V/sub th/, multiple-V/sub dd/ and standby leakage control techniques are presented.

Power minimization by simultaneous dual-V/sub th/ assignment and gate-sizing

Gate-sizing is an effective technique to optimize CMOS circuits for dynamic power dissipation and performance while dual-V/sub th/ (threshold voltage) CMOS is ideal for leakage power reduction in low voltage circuits. This paper focuses on simultaneous dual-V/sub th/ assignment and gate-sizing to minimize the total power dissipation while maintaining high performance. An accurate power dissipation model that includes short-circuit, switching, and leakage power is derived and used in our optimization. Results show that more than 20% and 10% power reductions are achievable for circuits at high and low switching activities, respectively, compared to single low-V/sub th/ CMOS circuits while maintaining performance.

Double gate dynamic threshold voltage (DGDT) SOI MOSFETs for low power high performance designs

In this paper, double gate dynamic threshold voltage (DGDT) SOI MOSFETs, which combine the advantages of DTMOS and FD SOI MOSFETs without the limitation of the supply voltage, are simulated using SOI-SPICE4.4. The threshold voltages, leakage currents and drive currents for FD SOI MOSFETs and DGDT SOI MOSFETs are compared. DGDT SOI MOSFETs show symmetric characteristics and the best I/sub on/I(off)/. Excellent DC inverter characteristics down to 0.15 V and good full adder performance at 1V are shown. The propagation delay and the average power consumption of the full adder are 0.625 ns and 11.5 /spl mu/W, respectively. It can be seen that DGDT SOI MOSFET is a good candidate for low power high performance designs.

Multiple-V/sub dd/ multiple-V/sub th/ CMOS (MVCMOS) for low power applications

In this paper, multiple-V/sub dd/ and multiple-V/sub th/ design techniques are combined to simultaneously achieve high performance and low power. The transistors in critical path(s) are assigned a higher supply voltage and a lower threshold voltage for high performance, while the transistors in non-critical paths may have a lower supply voltage and/or a higher threshold voltage to suppress dynamic power and leakage power. Accurate delay and power estimates using table look-up methods based on HSPICE simulations are used for supply voltage and threshold voltage optimization. Several algorithms for V/sub dd/ and V/sub th/ assignments under performance constraints are proposed and a genetic algorithm based vector control technique is presented for standby leakage reduction. For the ISCAS benchmark circuits, multiple-V/sub dd/, multiple-V/sub th/ CMOS (MVCMOS) design technique can reduce dynamic and leakage power dissipations by around 20% and 70%, respectively.

Design and optimization of double-gate SOI MOSFETs for low voltage low power circuits

With the growing use of portable and wireless electronic systems, design of high performance, low-voltage, low-power digital devices and circuits has become an important concern for VLSI applications. The double-gate (DG) fully-depleted (FD) silicon-on-insulator (SOI) MOSFET has an ideal subthreshold slope, high drive current and superb short channel effect immunity, which makes it very attractive in low-voltage, low-power, and high-performance CMOS designs. In this paper, by solving the Poisson equation, we propose a general model which has been verified by SOI-SPICE simulations. Based on this model, DGSOI MOSFETs are compared with conventional single gate FD SOI (SGSOI) MOSFETs, and the design and optimization of DGSOI MOSFETs in terms of circuit delay, power dissipation and power delay product are presented. In our analysis, we focus on FD DGSOI transistors without volume inversion, where the classical method is still valid.