Yibin Ye

Dynamic-sleep transistor and body bias for active leakage power control of microprocessors

Sleep transistors and body bias are used to control active leakage for a 32b integer execution core implemented in a 100nm dual V, CMOS technology. A PMOS sleep transistor degrades performance by 4% but offers 20/spl times/ leakage reduction which is further improved with body bias. Time constants for leakage convergence range from 30ns to 300ns allowing 9-44% power savings for idle periods greater than 100 clock cycles.

Design and optimization of dual-threshold circuits for low-voltage low-power applications

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

We describe various design automation solutions for design migration to a dual-Vt process technology. We include the results of a Lagrangian Relaxation based tool, iSTATS, and a heuristic iterative optimization flow. Joint dual-Vt allocation and sizing reduces total power by 10+% compared with Vt allocation alone, and by 25+% compared with pure sizing methods. The heuristic flow requires 5x larger computation runtime than iSTATS due to its iterative nature.

QSERL: quasi-static energy recovery logic

A new quasi-static energy recovery logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic styles are dynamic and require complex clocking schemes. The proposed QSERL uses two complementary sinusoidal supply clocks and resembles the behavior of static CMOS. Thus, switching activity is significantly lower than dynamic logic. In addition, QSERL circuits can be directly derived from static CMOS circuits. A high-efficiency clock generation circuitry, which generates two complementary sinusoidal clocks compatible to QSERL, is also presented in this paper. The adiabatic clock circuitry locks the frequency of clock signals, which makes it possible to integrate adiabatic modules into a VLSI system. We have designed an 8/spl times/8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 34% of energy over static CMOS multiplier at 100 MHz.

Mixed-V/sub th/ (MVT) CMOS circuit design methodology for low power applications

Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical paths, while a low-threshold is used in critical path(s) to maintain the performance. Mixed-V/sub th/ (MVT) static CMOS design technique allows different thresholds within a logic gate, thereby increasing the number of high threshold transistors compared to the gate-level dual threshold technique. In this paper, a methodology for MVT CMOS circuit design is presented. Different MVT CMOS circuit schemes are considered and three algorithms are proposed for the transistor-level threshold assignment under performance constraints. Results indicate that MVT CMOS design technique can provide about 20% more leakage reduction compared to the corresponding gate-level dual threshold technique.

A 256-Kb Dual-

This paper addresses the stability problem of SRAM cells used in dense last level caches (LLCs). In order for the LLC not to limit the minimum voltage at which a processor core can run, a dual-VCC 256-Kb SRAM building block is proposed. A fixed high-voltage supply powers the cache which allows the use of the smallest SRAM cell for maximum density, while a separate variable supply is used by the core for ultra-low-voltage operation using dynamic voltage and frequency (DVF). Implemented in a 65-nm bulk CMOS process, the block features low overhead embedded level shifters and an actively clamped sleep transistor for maximum cache leakage power reduction during standby. Measured results show that the proposed block runs at 4.2GHz while consuming 30 mW at 85degC and 1.2V supply. Furthermore, measurements across a wide range of process, voltage, temperature, and aging conditions indicate virtual ground clamping accuracy within a few millivolts of required cache standby VMIN. Extrapolating the 256-Kb block measurement results in a large 64-Mb LLC used in a dual-V CC processor gives 35% reduction in total processor power as compared with a single-VCC processor design running at a high supply voltage

{V}_{\rm CC}

Pulsed wordline (PWL) & pulsed bitline (PBL) techniques to improve SRAM cell stabilities in single-Vcc microprocessor designs are evaluated in 65nm CMOS. At 0.7V Vcc, PWL improves cell failure rate by 15times while incurring <1% area overhead. Both PBL & PWL with read-modify-write (PWL-RMW) provide the best improvements (26times) in cell stability, with significant area overheads (4-8%)

SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor

We present 2 Mb 2T PMOS gain cell macro on 65 nm logic process that has high bandwidth of 128 GBytes/sec, fast cycle time of 2 ns and 6-clock cycles access time at 2 GHz. Macro features a full-rate pipelined architecture, ground precharge bitline, non-destructive read-out, partial write support and 128-row refresh to tolerate short refresh time. Cell is 2X denser than SRAM and is voltage compatible with logic.

Wordline & Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65nm CMOS Designs

This paper compares different high-V/sub T/ and dual-V/sub T/ design choices for a large on-chip cache with single-ended sensing in a 0.13 /spl mu/m technology generation. The analysis shows that the best design is the one using a dual-V/sub T/ cell, with minimum channel length pass transistors, and low-V/sub T/ peripheral circuits. This dual-V/sub T/ circuit provides 20% performance gain with only 1.3/spl times/ larger active leakage power, and 2.4% larger cell area compared to the best design using high-V/sub T/ cells with nonminimum channel length pass transistors.

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology

Joint optimizations of dual-V/sub T/ allocation and transistor sizing reduce low-V/sub T/ usage by 36%-45% and leakage power by 20% in a high performance microprocessor, with minimal impact on total active power and die area. An enhancement of the optimum design allows processor frequency to be increased efficiently during manufacturing.