Zhanping Chen

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks

Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been verified by IISPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.

Design and optimization of dual-threshold circuits for low-voltage low-power applications

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

Design and optimization of low voltage high performance dual threshold CMOS circuits

Reduction in leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been verified by IISPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50%.

A power macromodeling technique based on power sensitivity

In this paper, we propose a novel power macromodeling technique for high level power estimation based on power sensitivity. Power sensitivity defines the change in average power due to changes in the input signal specification. The contribution of this work is that we can use only a few points to construct a complicated power surface in the specification-space. With such a power surface, we can easily obtain the power dissipation under any distribution of primary inputs. The advantages of our technique are two-fold. First, the required parameters corresponding to each representative point can be efficiently obtained by only one symbolic power estimation run or by only one Monte Carlo based statistical power estimation process. This stems from the fact that power sensitivity can be obtained as a by-product of probabilistic or statistical power estimation runs. Second, the memory requirements for the macromodel are reduced to O(dn), where n is the number of primary inputs of a circuit and d is the number of representative points (d can be as small as 1 in some cases). Results on a number of benchmark circuits demonstrate the effectiveness of our technique.

Power sensitivity—a new method to estimate power dissipation considering uncertain specifications of primary inputs

Power dissipation in CMOS circuits heavily depends on the signal properties of the primary inputs. Due to uncertainties in specification of such properties, the average power should be specified between a maximum and a minimum possible value. Due to the complex nature of the problem, it is practically impossible to use traditional power estimation techniques to determine such bounds. We present a novel approach to accurately estimate the maximum and minimum bounds for average power using a technique which calculates the sensitivities of average power dissipation to primary input signal properties. The sensitivities are calculated using a novel statistical technique and can be obtained as a by-product of average power estimation using a Monte Carlo based approach. The signal properties are specified in terms of signal probability (probability of a signal being logic ONE) and signal activity (probability of signal switching). Results show that the maximum and minimum average power dissipation can vary widely if the primary input probabilities and activities are not specified accurately.

Multiple-V/sub dd/ multiple-V/sub th/ CMOS (MVCMOS) for low power applications

In this paper, multiple-V/sub dd/ and multiple-V/sub th/ design techniques are combined to simultaneously achieve high performance and low power. The transistors in critical path(s) are assigned a higher supply voltage and a lower threshold voltage for high performance, while the transistors in non-critical paths may have a lower supply voltage and/or a higher threshold voltage to suppress dynamic power and leakage power. Accurate delay and power estimates using table look-up methods based on HSPICE simulations are used for supply voltage and threshold voltage optimization. Several algorithms for V/sub dd/ and V/sub th/ assignments under performance constraints are proposed and a genetic algorithm based vector control technique is presented for standby leakage reduction. For the ISCAS benchmark circuits, multiple-V/sub dd/, multiple-V/sub th/ CMOS (MVCMOS) design technique can reduce dynamic and leakage power dissipations by around 20% and 70%, respectively.

Sensitivity of power dissipation to uncertainties in primary input specification

To accurately estimate power dissipation, the exact signal probability (probability of a signal being logic ONE) and signal activity (probability of signal switching) of primary inputs are assumed to be known. In general, very accurate specification of primary input signal probability and activity may not be available. This in turn may result in uncertainties in average power estimation. In this paper we present a novel and efficient technique to estimate the sensitivity of average power dissipation to input signals using a symbolic estimation technique. Results for benchmark circuits show that power sensitivities can vary widely for different primary inputs of a circuit. Hence, in order to accurately estimate average power dissipation, the sensitive inputs of a circuit have to be specified accurately. We have also developed a Monte-Carlo based technique to estimate power sensitivity which also acts as a figure of merit for the symbolic technique.

On effective I/sub DDQ/ testing of low voltage CMOS circuits using leakage control techniques

The use of low threshold devices in low voltage CMOS circuits leads to an exponential increase in the intrinsic leakage current. This threatens the effectiveness of I/sub DDQ/ testing for such low voltage circuits because it is difficult to differentiate a defect-free circuit from defective circuits. Recently, several leakage control techniques have been proposed to reduce intrinsic leakage current, which may benefit I/sub DDQ/ testing. In this paper we investigate the possibilities of applying different leakage control techniques to improve the fault coverage of I/sub DDQ/ testing. Results on a large number of benchmarks indicate that dual threshold and vector control techniques are very effective in improving fault coverage for I/sub DDQ/ testing.

Efficient statistical approach to estimate power considering uncertain properties of primary inputs

Power dissipation in complementary metal-oxide-semiconductor (CMOS) circuits is heavily dependent on the signal properties of the primary inputs. Due to uncertainties in specification of such properties, the average power should be specified between a maximum and a minimum possible value. Due to the complex nature of the problem, it is practically impossible to use traditional power estimation techniques to determine such bounds. In this paper, we present a novel approach to accurately estimate the maximum and minimum bounds for average power using a technique which calculates the sensitivities of average power dissipation to uncertainties in specification of primary inputs. The sensitivities are calculated using a novel statistical technique and can be obtained as a by-product of average power estimation using Monte Carlo-based approaches. The signal properties are specified in terms of signal probability (probability of a signal being logic ONE) and signal activity (probability of signal switching). Results show that the maximum and minimum average power dissipation can vary widely if the primary input probabilities and activities are not specified accurately.

An efficient statistical method to estimate average power in sequential circuits considering input sensitivities

Power dissipation in CMOS circuits is heavily dependent on the signal properties of the primary inputs. Due to uncertainties in specification of such properties, the average power should be specified between a maximum and a minimum possible value. In this paper, we present a novel statistical approach to accurately estimate the maximum and minimum bounds for average power of sequential circuits using a technique which estimates the sensitivities of average power dissipation to primary input signal properties. The signal properties are specified in terms of signal probability (probability of a signal being logic ONE) and signal activity (probability of signal switching). The sensitivities are obtained as a by-product of the statistical power estimation technique using a Monte Carlo based approach. Results show that the maximum and minimum average power dissipation can vary widely if the primary input probabilities and activities are not specified accurately.