Liter Siek

A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning

A 7-GHz CMOS voltage controlled ring oscillator that employs multiloop technique for frequency boosting is presented in this paper. The circuit permits lower tuning gain through the use of coarse/fine frequency control. The lower tuning gain also translates into a lower sensitivity to the voltage at the control lines. Fabricated in a standard 0.13-mum CMOS process, the proposed voltage-controlled ring oscillator exhibits a low phase noise of -103.4 dBc/Hz at 1 MHz offset from the center frequency of 7.64 GHz, while consuming a current of 40 mA excluding the buffer.

Autonomous Wearable Sensor Nodes With Flexible Energy Harvesting

Distributed wearable wireless sensors are widely employed in wireless body sensor network for various physiological monitoring purposes like health or performance related monitoring applications. The real challenges in employing these wearable wireless sensors on human subjects include: 1) bulky and rigid system design thus, it is difficult to conform to human body contour and 2) limited operational lifespan of batteries with finite energy supply. In this paper, an autonomous body-worn wireless sensor node with flexible energy harvesting (FEH) mechanism, able to conform to body contour, is proposed for biometric monitoring. To be totally sustainable and compact, the FEH mechanism is equipped with an ultralow power management circuit (PMC) specially designed on a flexible PCB. The flexible PMC is able to transfer near maximum electrical power from the input solar energy source to store in the supercapacitor for powering the wireless sensor node. The power consumption of the flexible PMC is only 32.86 μW. Experimental results show that under indoor condition, typical average lighting intensity of 320 lux, the wearable sensor node is able to continuously monitor the temperature of the wearer, read, and transmit back to the base node in a wireless manner, without the need of any battery. In addition, the designed FEH sensor node flexed onto the wearer body contour at an angle of 30° generates 56 μW of electrical power, sufficient to sustain its operation for >15h.

A 400 nW Single-Inductor Dual-Input–Tri-Output DC–DC Buck–Boost Converter With Maximum Power Point Tracking for Indoor Photovoltaic Energy Harvesting

Energy harvesting enables the remote sensors of the wireless sensor network to obtain power from the environment for their entire lifetime. For indoor remote sensors, amorphous silicon photovoltaic (PV) cell can be used to harvest energy from indoor lighting. Furthermore, if the power consumption of the sensor is low, e.g., the image sensor in [1], the power rating of the PV cell can be limited to tens or hundreds of microwatts to minimize the form factor of the sensor. However, as the output power of the PV cell varies greatly with illumination level [2] and the output voltage of the PV cell (VPV), an energy storage device, such as a battery, is required to regulate the harvesters output power. Furthermore, a DC-DC converter with a maximum power point tracker (MPPT) is needed to lock the PV cell at its maximum power point (MPP).

Design of a High Performance Charge Pump Circuit for Low Voltage Phase-locked Loops

In this paper, the design of a 1.2 V charge pump circuit suitable for PLL-based frequency synthesizer with low spurious tone requirement is presented. The proposed charge pump circuit improves current matching in a wide output voltage range by applying a replica biasing technique with a new feedback structure that provides more stable operation. The systematic percentage error for the output range from 0.1 V to 1.1 V is less than plusmn0.5 %. Other non-ideal effects such as feed-through of the input pulses, charge sharing and timing mismatch of input signals are also significantly reduced. The charge pump circuit was designed in 0.18 mum CMOS process.

A 0.18-/spl mu/m 10-GHz CMOS ring oscillator for optical transceivers

This paper presents a three-stage 1.8-V 10-GHz ring oscillator, implemented using the 0.18-/spl mu/m digital CMOS technology. The circuit utilizes the feedforward technique at the delay cells and positive feedback provided by a cross-coupled nMOS pair in each delay cell to boost the operation speed of the oscillator. The output frequency ranges from 10.1 to 8.4 GHz with control voltages of 0 to 1.5 V. The simulated result of the phase noise is -99.9 dBc/Hz at 1-MHz offset from the center frequency of 9.2 GHz. The circuit draws 35 mA and 22 mA from the 1.8-V supply when running at the highest and lowest frequencies, respectively.

Adaptive Gate Switching Control for Discontinuous Conduction Mode DC–DC Converter

This paper aims to develop a novel adaptive gate switching controller (AGSC) for discontinuous conduction mode (DCM) dc-dc converters, in an attempt to reduce the power losses caused by nonideal gate switching operations. The proposed AGSC employs a dead-time controller (DTC) and a zero-current detector (ZCD) to turn ON and OFF the synchronous switch, respectively. Both the DTC and the ZCD perform self-calibration according to the converter switching node voltage, allowing the AGSC achieves near-optimal gate switching control regardless of the operating frequency, process variation, power device variation, as well as source voltage and load current variation. The proposed AGSC can have useful applications in many DCM dc-dc converters, e.g., buck, boost, and buck-boost converters. For a proof of concept, in this paper, a boost converter was implemented with the proposed AGSC in a 0.18-μm 3.3-V CMOS process with an area of 1.5 mm 2 . The experimental results demonstrate precise control of the gate switching operations, and the boost converter at 1.2-V/2.5-V nominal input/output achieves a peak efficiency of 86% at 30-mA load current.

Single inductor quad-input-dual-output buck converter for photovoltaic systems

Stand-alone photovoltaic (SAPV) system is more favourable than grid connected photovoltaic (PV) system in areas where extension of power grid is impracticable. However, the high set up cost of a SAPV system requires cost efficient solar energy harvesting methods. To improve the energy harvesting efficiency of a PV system, a large, centrally controlled PV array can be rearranged into smaller PV modules that are individually controlled to operate at its respective maximum power point (MPP), thus forming a modular SAPV system. However, the implementation cost of the modular SAPV system is higher due to the increase in component count. We propose to reduce the component count of a modular SAPV system by utilizing a single-inductor multiple-input-dual-output converter. In this paper, a single inductor quad-input-dual-output DC/DC buck converter (QIDO) is proposed. Simulation results verified that a QIDO could regulate three PV modules independently, so that each PV module could operate at its MPP. Results also proved that a QIDO could regulate the power delivered to the load by diverting excess PV power to recharge the battery and drawing supplementary battery power when PV power was inadequate. In summary, the cost efficiency of a modular SAPV system, comprising of three PV modules, a battery and a load can be improve replacing four DC/DC converters by a single QIDO, which results in a 56.25% reduction in the components required.

A compact current mode neuron circuit with Gaussian taper learning capability

In this paper, an analog current mode implementation of a neuron circuit capable of performing real Gaussian neighborhood taper learning is presented. The neuron cell is compacted with a reusable multiplier that can function as squarer and multiplier for Euclidean and topological distances calculation as well as for Gaussian function characteristics with adjustable learning rate. A four-neuron self-organizing map (SOM) with three dimensional input data is designed and simulated using CSM 0.18 µm technology to demonstrate the learning control and neighborhood adaptation. The network can process 4.55 million vectors per second with a minimum power consumption of 1.6mW at 1.5V.

A high frequency, high efficiency GaN HFET based inductive power transfer system

This paper aims to develop an Inductive Power Transfer (IPT) system targeting at Electric Vehicles (EV) and Hybrid Electric Vehicles (HEV). IPT systems provide significant benefits over conventional plug-in chargers. However, in order for IPT to be adopted for EV charging, efficiency is a key Figure of Merit (FOM) which needs to be achieved. This paper develops an inverter using Gallium Nitride (GaN) power transistors which have the benefit of low on-resistance and gate charge to reduce the switching and conduction loss. A design methodology for optimising the switching performance of the power transistor is developed in order to minimise switching loss while keeping overshoot under control. An efficiency centric control method is proposed to improve the efficiency of the system, while ensuring sufficient power transfer. The evaluation results show that a GaN based system is capable of outperforming a SiC based system. At a gap of 150mm, the system obtains above 90% efficiency at 1.3 kW. The system efficiency peaks at 95% at 100 kHz operation and 92% at 250 kHz operation at a distance of 80mm for 2kW output power.

An ultra low-power rail-to-rail comparator for ADC designs

This paper presents a novel ultra low-power rail-to-rail comparator which can be suitably used in low-to-medium speed A/D converters. This comparator adopts a preamplifier followed by a dynamic latch structure to achieve fast-decision, high-resolution as well as reduced kick-back noise. A new adaptive power control technique is used to reduce the power consumption of the preamplifier. The circuit is designed and simulated in Global Foundries 65nm CMOS technology. The simulation results have shown that the power consumption of 12-bit comparator is 191.2 nW at the clock frequency of 15 MHz and 0.8 V supply voltage with a delay of 1.17nS.