Liu Zhaoqing

A Design of Multiprotocol Asynchronous Serial Communication Based on M Module

This paper proposes a design of multi protocol asynchronous serial communication M module, which can be configured as 8-channel RS-232 or 4-channel RS-422/485, and each channels property including baud rate, character-bit, parity mode and stop-bit can be configured separatly through the software. FPGA is adopted as the development platform, using the Verilog HDL to design timing logic of Mbus interface, UART (universal asynchronous receiver transmitter) and control logic of transceiver. This module with multifunction and flexibility, applies to VME, VXI, PXI, LXi and other bus sys-tem. The paper gives the hardware design and driver functions interface. The experimental result indicates that the module works stably, meets the reliability, functional and general requirements.

Parallel Processing Design of Multi-channel LIF Digital Receiver

This paper presents a design method for parallel multi-channel low-intermediate-frequency (LIF) digital receiver. It is based on the DSP sub-array with a simple topology and operation timing to evaluate and determine the processing capability and then construct the parallel processing array for multi-channel signals according to the restriction of operation timing. With this method the design of multi-channel digital receiver may be simplified. As an example, a design of shortwave band receiver is used to show how to apply this method

Design and implementation of a certain type of missile timing sequence testing system

Timing sequence test is a core part for missile ground testing, the results directly determine whether the missile can be well launched. A specialized CPCI timing sequence testing system for missile is presented in this paper, which is able to complete the sequence test of tail boot, gesture controller, sequence circuit, instant flight for both equivalent device and actual missile. Also, the design of structure, firmware, driver and host computer software of the sequence test system are described in details. The experimental results show that the system is stable and efficient, conforming to the design requirements.

M-Module Carrier Based on PCI Bus

Based on the detailed analysis of M-Module specification and PCI specification, this thesis design a kind of M-Module carrier which based on PCI bus. The design use FPGA as core controller in the design of hardware to decrease difficulty and cost. The design used IP core to control PCI interface and developed firmware for M-Module interface. This design solved a series of problems such as the problem of the address not matching, fast data transmission, data select table simplification etc. The M-Module carrier supports normal reading and writing, burst transmission, asynchronous event trigger function, interrupt handling, DMA transmission of M-Module. The carrier also supports the auto-adaptation and auto-configuration functions of M-Module. Within the software design, this thesis proposes standard software architecture and design reasonable functions to operate the M-Module interface and completes the design of general purpose Low-Level driver of M-Module carrier.

A Design of Testing Platform for Seeker Based on Embedded System

This paper proposes the idea of designing an testing platform for seeker to the core of embedded system. Through generalizing the testing requirements, the adapting interface of data acquisition, storage, transmission and displaying are devised reasonably. The dual core structure of ARM9 and FPGA is applied in the hardware design, and the software adopts embedded Linux operating system, when multi-thread programming technique is used in application. Practice shows that this platform has the advantage of abundant interfaces, diverse function and flexible scalability, which can meet all the need of testing task of seeker.

Design and application of LXI instrument based on script-download and module-to-module communication

LXI (LAN eXtensions for Instrumentation) Specification provides test instrument and system with a set of new functions, which enable instruments and systems based on LXI complete more complex test tasks. With these new functions, users can build more intelligent system architecture, further improve the automatic test system (ATS) commonality and performance. Downloading executable code and module-to-module communication are two key technologies which defined by LXI Specification. This paper addresses these two technologies, and builds a test system to demonstrate their advantages.

Design of 4-Channel Asynchronous Serial Communications Interface

Asynchronous serial communications are frequently used for data exchange between test system and the peripheral to be tested in research and development of automatic test systems. However, in most conditions, a test system with a single CPU can not meet the demand of multi-channel asynchronous serial communications. In the design of an automatic test system that takes FPGA+DSP as its core architecture, we develop a new approach to 4-channel serial interface based on the asynchronous communications element (ACE) TL16C554, which makes 4-channel full duplex asynchronous serial communications possible. In this paper, the structure and characteristics of ACE TL16C554 are introduced at first, and then the design of the interface is described in detail according to the serial communications protocols. The interface controller is implemented in FPGA in Verilog HDL and the initialization of the ACE is conducted by DSP. It has been demonstrated that the 4-channel asynchronous serial interface works stably and reliably.

A LXI bus interfaces hardware design method with the SOPC

A hardware design method of LXI bus interface using FPGA-based SOPC is presented in this paper. The NIOSII core from AlteraTM was taken to implement the control logic of the LXI C-Class interface. And the DPE-1588IP core was chosen to achieve the design of LXI B-class interface, in which the IEEE 1588 high-precision time protocol required by the specifications was realized. While such a B-class interface is connected to an industry standard Gigabit Ethernet PHY device, Gigabit network speed suggested in the LXI specifications can be reached. As for the hardware trigger bus of the LXI A-class interface, the SN65MLVD200A was adopted to make half-duplex, M-LVDS trigger bus interface. Besides the above functions, the NIOS core can also be used to control the functional circuit in LXI devices.