Qiao Liyan

Realization of high speed mass storage Data Record Card with CF Card and SDRAM

This paper presents a design that realizes a dual-channel Data Record Card which achieves 33MB/s data transfer rate and 4GB capacity per channel with CF Card and SDRAM. According to the characteristics of data transfer with CF Card, an advanced data transfer method is provided, which reduces the requirements of memory resources in FPGA without influencing the data transfer rate. And it realizes high speed data transfer between CF Card and low-end FPGA with limited memory resources.

Blind separation of speech sources in multichannel compressed sensing

This paper presents a novel framework for separating and reconstructing multichannel speech sources from compressively sensed linear mixtures simultaneously. The conventional approaches for blind speech separation are almost based on the Nyquist sampling theory. We proposed an approach which uses the multichannel compressive sensing theory for blind speech separation. The linear programming and gradient-based methods are used to separate the sources. Compared with the conventional blind speech separation, the proposed approach can reduce the requirements of sampling speed and operating rate of the devices. Moreover, our approach has lower computational complexity. The main contribution of this paper lies in proposing a novel procedure to estimate the sources from the measurements without reconstructing the mixed signals. Simulation results demonstrate the proposed algorithm can separate multichannel speech sources successfully.

Sparsity-based radar signal sorting method in electronic support measures system

In view of low radar signal sorting accuracy in electronic support measures system (ESM), a new sparsity-based radar signal sorting method is put forward in this paper. Firstly, the pulse description words (PDW) of radar pulse sequence are analyzed and normalized, and then represented as a sparse linear combination of the sparse representation dictionary. Secondly, the sparse solution is calculated by solving an optimization problem under L1 norm. Finally, the linear correlation coefficients between the sparse solutions of test sample and standard samples are calculated and compared to determine the classification of radar signal. The experiment result showed that the radar signal sorting accuracy of this method is 96%, and the performance of the method is superior to other radar signal sorting algorithms. So this sparsity-based radar signal sorting method has high accuracy and strong anti-noise interference ability.

Method of LFM pulse compression implementation based on FPGA

For the achievement of LFM signal acquisition, pulse compression and storage, the hardware platform is built. A way to implement the pulse compression of the LFM signal based on FPGA is presented. This paper describes in detail the functions and implementation methods of the various functional modules of the FPGA in the pulse compression process. A theoretical simulation on the pulse compression is done, and the actual test results are analyzed after compared with the theoretical simulation.

Design of generic embedded memory built in self test circuit

With the increment of area of memory in SoC, embedded memory test is becoming increasingly significant. The March algorithm and its derived algorithms, which are the mainstream algorithm in memory test domain, can achieve very good effects in terms of testing time and fault coverage. However, because of the different accesses of different types of memories, the same algorithm cannot apply to testing different types of memories. In SoC, implanting different circuits for testing different types of memories will result in high hardware overhead. To solve this problem, we design a generic embedded memory built-in self-test circuit which, according to different types of memories, chooses the suitable testing algorithms through configuring a set of March algorithm registers. This method will make the testing circuit adapt to different types of memories and the corresponding hardware overhead is relatively low. Verified by Modelsim simulation, this method has a flexible configuration and has a high coverage of common faults.

Stereo matching using pixel classification and dual-weighted guided filter

Finding the subjectively correct binocular disparity of a stereopair has long been a challenging issue for researchers. A coarse-to-fine algorithm is presented in this article for seeking to a more reasonable solution to this issue. We focus on the disparity computation other than disparity refinement and post-processing procedures. Dual-weighted guided filter or a simplified guided image filter with dual-weights is proposed to boost computation efficiency and reduce matching ambiguity. Perceived as a classification step, a normalized cross-correlation based method aims for searching for reliable matching candidates. Three channels in RGB colour space are biologically weighted for subjectively rational correspondence. As comparative experimental results show, the proposed method performs excellently without post-processing. All the algorithms are tested on Middlebury stereopsis benchmark.

BPM: A Bad Page Management Strategy for the Lifetime Extension of Flash Memory

The lifetime of NAND flash is highly restricted by bit error rate (BER) which would exponentially increase with the number of program/erase cycles. While the error correcting codes (ECC) can only provide a limited error correction ability to tolerate the bit errors. To face this challenge, a novel bad page management (BPM) strategy is proposed to extend the lifetime of NAND flash based on the experimental observations in our hardware-software co-designed experimental platform. The experimental observations indicate that retention error is the dominant type of NAND flash errors, which is caused by the charge leakage in memory cells over time. The BER distribution of retention error shows distinct variance in different pages. The key idea of BPM is to excavate lifetime potency of each page in a block by introducing the fine granularity bad page management instead of the coarse granularity bad block management. In addition, to balance the lifetime enhancement and the storage capacity degradation, a configurable threshold of bad page management (CT-BPM) strategy is proposed to utilize in the storage capacity highly demanded applications. The experimental results show that BPM can provide dozens of times (about 35 times for 3x-nm NAND flash) average lifetime extension without additional hardware cost, while experiencing at most 5% degradation in writing speed.Copyright

Development of high-speed data acquisition card based on PXI Express Bus

This paper develops a high-speed data acquisition card based on PXI Express Bus, with 1.5GSa/s dual-channel sampling rate and 3GSa/s single-channel sampling rate, 8-bit of resolution, and 1GB of high-speed data cache. In the paper, an overall scheme of the system is presented, ADC08D1520 is utilized to realize the acquisition of dual channel/single channel signal, DDR2 SDRAM is used as the large-capacity data buffer, and PCI Express Endpoint Block is adopted to realize the protocol of the PCI Express Bus. The paper also proposes two data transmission schemes based on PCI Express Endpoint Block to improve the efficiency of data transmission. One is DMA engine, another is Peer-to-Peer Engine. The PXI Express driver which supports the DMA and interrupt is developed by NI-VISA. At last, the performance testing of the card is presented. The testing results show that this computer-based high-speed card offers an outstanding combination of high bandwidth (up to 800MHz) and dynamic range, which enables demanding measurements such as IF sampling of wide band signals.

A sub-Nyquist sampling spectrum sensing system based on PXI bus for multiband signals

In this paper, a sub-Nyquist sampling system for multiband signals is presented, which can perform accurate spectrum sensing and reconstruction. The system is based on PXI bus and virtual instrument technology, which make the proposed system able to be adjusted flexibly for different input signals. Compressive sensing (CS) theory and modulated wideband converter (MWC) are adopted in the system. The detailed design process of the system is given in the paper. The extension method of observation matrix and the reconstruction algorithms are also explained in this paper. Experimental results show that the proposed system can sample the multiband signal at an extreme low frequency and recover the signal spectrum effectively.

A TPS Integrated Development Environment implementing IEEE1641 and ATML

With the publication of IEEE1641 and Automatic Test Markup Language (ATML), high level solutions to instrument interchange problem can be accomplished in the near future. This paper introduced a TPS (Test Program Set) Integrated Development Environment (IDE), including a Graphical Signal and Test definition application and an ATML Executive Environment. Experiment shows the TPS IDE can reduce development time and maintenance of test system.