Erwan Fabiani

Placing, Routing, and Editing Virtual FPGAs

This paper presents the benefits of using a generic FPGA tool set developed at the university of Brest for programming virtual FPGA. From a high level description of the FPGA architecture, the basic tools such a placer, a router or an editor are automatically generated. The description is not constrained by any model, so that abstract architectures, such as virtual FPGAs, can directly exploit the tool set as their basic programming tools.

Intermediate Level Components for Reconfigurable Platforms

Development productivity is a central point for the acceptance of reconfigurable platforms. Due to the availability of generic low level tools and powerful logic synthesis tools, it becomes possible to define portable components that have both a high level behavior and attributes for physical synthesis. The behavior of a component can be fixed at compile time using concise specifications that will reduce the cost and delays in developments. The method allowing to produce components is illustrated with two case studies.

Placement of Linear Arrays

This paper presents a methodology for mapping linear processor arrays onto FPGA components. By taking advantage of regularity and locality properties of these structures, a placement is pre-defined, allowing vendor tools to skip this phase and produce fast and optimized routing.

Asserting causal properties in High Level Synthesis

ICs are subject to many causes of malfunction such as aging or aggressive environment, while avoiding unwanted behavior of critical applications is a key issue. Monitoring is a cornerstone of safety policies, as it supports triggering counter measures on demand. High Level Synthesis (HLS) allows to easily implement applications in hardware, and some HLS compliant solutions have been reported. These solutions monitor applications through asserting properties to variables. This paper extends this approach by proposing causal assertions, dedicated to monitoring the evolution of variables over time. Results demonstrate significant gains in term of reactivity and error coverage rate, while keeping the overhead low.

Modeling Sensor Networks as Concurrent Systems

The poster will illustrate the methodology synthesizing random topologies into working traceable concurrent programs. In the future, automatic synthesis of code or hardware transition functions will be addressed using tools such as Handel-C, or Madeo.

Synthèse portable pour micro-architectures à grain fin : Application aux turbo décodeurs et nanofabriques

Reconfigurable architectures are similar. To ease their sof ware integration, the Madeo framework proposes a common model used by generic CAD t ools. The development of high level tools can rely on an open synthesis layer with be havioural and structural aspects. The capability for fast integration of technologies is show n of the case of early investigations on nano-fabrics, while the efficiency of the synthesis is demon strated on parts of a turbo decoder known to be critical in communications.