Marc D. Rosales

Design and implementation of operational amplifiers with programmable characteristics in a 90nm CMOS process

Operational amplifiers (op-amps) serve as the basic building blocks in almost every analog and mixed-signal electronic circuit. However, one of the most common problems in op-amp design is the variation in the op-amps performance caused by process variations during fabrication. As such, it is of utmost importance that provisions be made on the op-amp to compensate for possible deviations in performance after chip fabrication. In this paper, a procedure on integrating programmable bias networks into an operational amplifier is developed. The programmable network driven by digital input words makes the output bias currents and voltages variable, thus making the op-amp tunable for proper operation even after chip fabrication. Furthermore, the programmability of other op-amp parameters such as gain, slew rate, and compensation are explored to increase the capability and flexibility of the op-amp. The programmability schemes are employed on two base op-amp topologies namely, the Two-stage Miller and the Folded Cascode. The project is implemented in a standard 90nm CMOS process.

Design and implementation of CMOS rail-to-rail operational amplifiers

The paper presents the design and implementation of six operational amplifiers with rail-to-rail input and output capability. The study characterizes several rail-to-rail input and output stages and the dependence of the op-amps operation on different design parameters to formulate a standard design methodology that can serve as a guide for future researches and projects in the area of rail-to-rail amplifiers. The report shows the effects of the rail-to-rail stages on the op-amps input common-mode range and output voltage swing range. The op-amps are implemented in 0.25 mum CMOS process and the simulation results achieve specifications such as gain, bandwidth, offset voltages and common-mode rejection ratio comparable with commercially available circuits.

Opto-microwave experimental mapping of SiGe/Si phototransistors at 850 nm

This paper presents measurement results providing the mapping of the opto-microwave transfer function performed on an SiGe microwave heterojunction phototransistor (HPT). This measurements will be used to extract a guideline for designing phototransistors. A mapping of the HPTs gain in low frequency helps to estimate the shape of the optical beam used for the measurement. The study also focuses on the cutoff frequency mapping of the device in phototransistor mode. Finally, these results are used to determine the general optimization rules in the SiGe HPTs design.

Design and implementation of SiGe HPTs using an 80GHz SiGe bipolar process technology

We present the design and characterization of SiGe Heterojunction Phototransistors using an 80GHz commercial SiGe Bipolar process. It is shown that 50µm HPTs are exhibits highest gain.bandwidth product of 0.8GHz.A/W compared to the 10µm HPTs

Full area emitter SiGe phototransistor for opto-microwave circuit applications

We present a study of full area emitter phototransistors with different optical window sizes implemented in a SiGe Bipolar technology. Extracted responsivity of 3.5 A/W and an opto-microwave cut-off frequency of 739 MHz were observed.

Comparison between two 60GHz multipoint RoF architectures for the Home Area Network

60GHz radio coverage is extended using low-cost multipoint-to-multipoint RoF architectures based on optical or electrical splitter. These infrastructures are compared in terms of EVM and real-time signals transmissions between commercial devices working at 3Gbit/s. Finally, improvements based on innovative SiGe photoreceptors are proposed.

De-embedding Techniques on a 0.25 μm Digital CMOS Process

Fully intregrated radio frequency circuits require the use of several passive devices. In designing these circuits, there is a need to know how these circuit elements behave. Inductors implemented on silicon are not easily characterized compared to their discrete counterparts. On-wafer measurement is necessary to understand the characteristics of these inductors that are implemented on silicon. This will give a better insight in the design of RF circuit that will utilize these components. In this study, several inductor structures were fabricated on a 0.25 μm CMOS process which will serve as the device under test (DUT). Open, Short1, Short2 and Thru structures were also implemented to characterize the different OPEN and THREE step de-embedding techniques

Monolithic Spiral Inductors for a 0.25 μm Digital CMOS Process

The digital CMOS processes currently enjoys a continued scaling in feature sizes. This allows the the process to have transitors that are viable to be used for RF circuits. This has fueled a lot of research focused on using CMOS technology to implement RF circuits. Inductors are present in most of the RF circuit modules and oftentimes consume large areas on silicon. However, the lack of models that will accurately predict their behavior on silicon using a CMOS process presents a major limitation in the full integration of RF systems on CMOS. These inductors are characterized using an inductor model to effectively compare the merits of each implementation and to identify relevant parasitics that limit the performance of these inductors.

Integrating spiral inductors on 0.25 /spl mu/m epitaxial CMOS process

In this study, different spiral inductor implementations are compared. Q enhancement techniques are also evaluated in minimizing inductor losses on a 0.25 /spl mu/m epitaxial CMOS process. Inductor coupling between adjacent inductors was also considered in this study by measuring the S/sub 21/ parameter between the inductors implemented. Reported structures that minimize inductor coupling and layout strategies are explored in reducing coupling. From measured results, octagonal spiral inductors have higher Qs compared to square spirals. Results from the study have shown that patterned ground shields not only improve inductor Q but also limit inductor coupling. In integrating multiple inductors, a diagonal configuration improves isolation by at least 5 dB when compared to a horizontal configuration.

Monolithic CMOS Current-Mode Instrumentation Amplifiers for ECG Signals

In this paper, four monolithic current-mode instrumentation amplifier (in-amp) topologies are implemented in 0.25um CMOS process, with positive second-generation current conveyors (CCII+) as building blocks. The in-amp topologies are designed to handle biomedical signals, specifically that of the Electrocardiogram (ECG). Four types of CCII+ are characterized and realized using a rail-to-rail op-amp and different types of current mirrors. The Op-Amp with Simple Current Mirror exhibits the highest current swing and the lowest power consumption, and is thus chosen as the optimum CCII+ block to be used in all four in-amps. All current-mode in-amps are implemented using a standard 0.25um CMOS process and yield excellent common-mode rejection ratio (CMRR) greater than 150dB for a differential gain of 100. All four in-amps consumes less than 2.5mW of power for a single voltage supply of 2.5V. However, the 2-Current Conveyor with Op-Amp at the Output (2-CC with Op-Amp) has adjustable output reference voltage and provides the lowest output impedance among the four in-amps.