Lourans Samid

A multibit continuous time sigma delta modulator with successive-approximation quantizer

This paper discusses the design of a multibit sigma-delta modulator using a continuous time (CT) loop filter and a successive approximation (SA) A/D converter as multibit quantizer instead of the usual flash converter. This results in reduced circuit complexity as well as lower power dissipation and area. Measured results of a second order CT modulator with three bits quantizer show 58 dB SNR and 120 muW power dissipation with an OSR of 16 and a power supply equal to 1.5 V

A dynamic analysis of a latched CMOS comparator

In the implementation of high-performance CMOS over-sampling A/D converters, high-speed comparators are indispensable. This paper discusses the design and analysis of a low-power regenerative latched CMOS comparator, based on an analytical approach which gives a deeper insight into the associated trade-offs. Calculation details and simulation results for a 20 MHz clocked comparator in a 0.5/spl mu/m technology are presented.

Multirate cascaded continuous time /spl Sigma//spl Delta/ modulators

Cascaded continuous time sigma-delta (/spl Sigma//spl Delta/) modulators provide a favourable way to achieve high resolution, high speed A/D converters. This paper presents a way to upgrade the advantages further by using multirate cascaded continuous time modulators. Therewith high resolution can be achieved with even lower oversampling ratio and therefore lower power consumption than in the single rate case. Here we show the successful synthesis of a multirate cascaded (2-1) continuous time /spl Sigma//spl Delta/ modulator. The performance is analyzed theoretically and by simulations. Finally it is shown what speed forfeits we have to own up to. It will be shown that multirate cascaded continuous time /spl Sigma//spl Delta/ modulators are useful to achieve high speed, high resolution A/D converters.

A new kind of low-power multibit third order continuous-time lowpass /spl Sigma//spl Delta/ modulator

This paper presents the design of a multi-bit-third-order low pass sigma-delta modulator using a continuous-time (CT) loop filter. The goal is to reduce the power consumption and the area of the modulator. The new notion is to use a successive approximation (SA) A/D converter as 4-bit quantizer in the sigma-delta-modulator. Simulation results of the CT sigma-delta modulator show a 95 dB signal to noise ratio in a bandwidth of 50 kHz and oversampling ratio (OSR) of 32.

Implementation of a 1.5V low-power clock-jitter insensitive continuous-time /spl Sigma//spl Delta/ modulator

The design of a low-power clock-jitter insensitive continuous-time /spl Sigma//spl Delta/ modulator is presented. The circuit uses a time-variant feedback digital-to-analog converter (DAC) to reduce the clock jitter influence. Special care was taken to the overall power consumption of the modulator. In order to show the power efficiency of this technique in comparison to the standard non-retum-to-zero DAC, behavioral simulations considering finite DC-gain, GBW and slew-rate were done. Additional it will be shown that the proposed concept is suitable for very low supply voltages. The modulator operates at a 1.5V power supply and achieves a signal-to-noise+distortion-ratio (SNDR) of 70dB for a 25kHz signal bandwidth. The test chip was realized in a 3.3V, 0.5-/spl mu/m CMOS DPTM process.

An ultra low power continuous-time sigma delta modulator

This paper presents the design of a continuous time third order low pass sigma delta /spl Sigma//spl Delta/ modulator. The loop filter has been implemented by using an active RC-integrator in the first stage and a transconductance-capacitor (G/sub m/-C) integrator in the second and third stage. The influence of the low supply voltage on the building blocks, such as the amplifier and the common mode feedback, as well as the distortion of the G/sub m/-cells on the overall /spl Sigma//spl Delta/ modulator are discussed. Simulation results of the 1.5 V CT /spl Sigma//spl Delta/ modulator show a 60 dB SNDR in a bandwidth of 50 kHz and a sampling frequency equal to 3.2 MHz. The power consumption is 50 /spl mu/W.

The nonidealities of multibit continuous-time sigma delta modulators

This paper discusses the influence of nonidealities on the continuous time multibit sigma delta modulators, such as clock jitter and RC-tolerance. Another aspect that is discussed in this paper is the power dissipation of the modulator with RZ- and NRZ-feedback realization. Calculation details and simulation results for a low-pass continuous time third order sigma delta modulator with an oversampling ratio of 32 are presented.

Successful design of cascaded continuous-time /spl Sigma//spl Delta/ modulators

This paper presents a method for the successful design of high resolution cascaded continuous time EA modulators. Therefore performance limiting aspects are considered analytically and through simulation. A previously introduced simple method for RC-error cancellation is investigated and extended to cancel errors due to finite gain bandwidth. Finally we present a high-level system, which can be integrated following the proposed way to achieve high-performance cascaded continuous time modulators.

A low power and low voltage continuous time /spl Sigma//spl Delta/ modulator

This paper discuses the design strategy and implementation of a very low power and low voltage oversampling A/D converter based on a continuous time /spl Sigma//spl Delta/ modulation. The influence of several design parameters like RC-tolerance, clock jitter and implicit anti-aliasing filter are treated. Measurement results of a 1.5 V single bit third order continuous time /spl Sigma//spl Delta/ modulator show a 61 dB SNDR in 50 kHz signal bandwidth and a sampling frequency equal to 3.2 MHz with a power consumption of 78 /spl mu/W.