Friedel Gerfers

A continuous-time /spl Sigma//spl Delta/ Modulator with reduced sensitivity to clock jitter through SCR feedback

This paper presents a means to overcome the high sensitivity of continuous-time sigma-delta (/spl Sigma//spl Delta/) modulators to clock jitter by using a modified switched-capacitor structure with resistive element in the continuous-time feedback digital-analog converter (DAC). The reduced sensitivity to jitter is both simulated and proven by measured results from two implemented third-order modulators. Additionally, the nonideal behavior is analyzed analytically and by simulations.

Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators

This paper introduces a possible compensation for finite gain-bandwidth (GBW) induced errors in continuous-time sigma-delta modulators. Therefore, a novel model is derived which reduces the effect of a finite GBW to a corresponding integrator gain-error and feedback loop delays. Thus, previously published methods for the compensation of these errors can be adopted with some modification. The results are confirmed analytically and by simulations and show a possible GBW reduction of about one order of magnitude compared to current designs.

A case study on a 2-1-1 cascaded continuous-time sigma-delta Modulator

This paper intends to give an insight into the potentials and tradeoffs when designing cascaded, continuous-time (CT) sigma-delta modulators. Therefore, a case study is presented considering the implementation of a 2-1-1 CT modulator. The nonideal behavior is regarded in detail and an automatic gain-error cancellation is presented. Finally, a circuit board implementation is presented, which has been chosen to verify the automatic error correction. It turns out that despite a more critical behavior than in the discrete-time (DT) case, cascaded CT modulators have the potential, to realize high bandwidth, high resolution analog-to-digital (A/D) converters in future integrated designs.

On the Implicit Anti-Aliasing Feature of Continuous-Time Cascaded Sigma–Delta Modulators

This paper deals with one of the most outstanding advantages of continuous-time (CT) sigma-delta modulators compared to their discrete-time counterparts: the implicit anti-aliasing feature (AAF). Although inherent in any CT architecture, analysis of anti-aliasing properties has mostly been restricted to single-stage modulators in the past. In this contribution, extensions on analysis methods for the study of the AAF of CT multistage noise-shaping architectures are covered. A theoretical model is introduced and confirmed through simulation results. Contrary to previous belief, the results indicate that usually all stages of a cascaded architecture are involved in the anti-aliasing behaviour and hence that it is not solely determined by the first stage.

A design strategy for low-voltage low-power continuous-time /spl Sigma//spl Delta/ A/D converters

This paper presents a design strategy for low-voltage low-power /spl Sigma//spl Delta/ analog-to-digital (A/D) converter using a continuous-time (CT) lowpass loop filter. An improved method is used to find the optimal /spl Sigma//spl Delta/ modulator implementation with respect to a minimal power consumption on the one hand and to fulfil a rapid prototyping approach on the other hand. The influence of the low supply voltage as well as circuit nonidealities on the overall /spl Sigma//spl Delta/ modulator is determined and verified by behavioral simulations. Transistor-level simulation results of a 1.5 V CT /spl Sigma//spl Delta/ A/D converter show a 75 dB dynamic range in a bandwidth of 25 kHz.

Influence of finite integrator gain bandwidth on continuous-time sigma delta modulators

This paper presents analytical considerations on the gain-bandwidth requirements in continuous-time /spl Sigma//spl Delta/ modulators with rectangular and decaying feedback pulse forms. Therefore the influence of finite GBW is modelled as an integrator gain error and an additional loop delay in the feedback path, or as a slowdown of the feedback slope respectively. The presented models provide a very good insight into the influence of finite gain-bandwidth on the performance of continuous-time modulators. Additionally it could be shown, that the bandwidth can be chosen much lower as usually done in designs, and moreover, that it should be possible to reduce its influence by coefficient tuning. Both, the model and the analytical considerations are proven by simulations.

Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators

This paper examines the influence of different clock jitter forms on the performance of discrete-time and continuous-time sigma-delta modulators, the latter with rectangular and with decaying feedback pulse form. It could be shown that the so called accumulative clock jitter from a VCO is the fundamental, performance limiting factor for all architectures, which can not be circumvented, limiting the maximum achievable signal-noise ratio.

A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller

High density 48-port network switches demand very power-efficient, small form-factor physical layer transceivers which comply with the transmit PSD and return loss requirements, on the one hand, and meet the FCC Class-A specifications on the other hand, while achieving better than 10E-12 BER. The presented 10GBASE-T transmitter and hybrid utilize a current-mirroring amplifier with output rise-time control and high CMRR to perform a first-order linear and nonlinear echo cancellation while enabling the design of 48-port FCC compliant network switches. Experimental results over the 400-MHz bandwidth exhibit a worst case transmitter linearity of >;57 dBc as well as worst case post-hybrid fundamental and SFDR power of -18 and -70 dBc, respectively, across the 400-MHz frequency range of interest. The echo fundamental component is further attenuated to <; -60 dB in the analog domain by an adaptive mixed-mode echo canceller. Implemented in a 40-nm CMOS technology, the transmitter plus hybrid consumes 200 mW power and occupies 0.5 mm2.

Figure of merit based design strategy for low-power continuous-time /spl Sigma//spl Delta/ modulators

This paper presents a novel design strategy for low-power continuous-time (CT) /spl Sigma//spl Delta/ modulators. The figure of merit (FOM) is used to find the optimal /spl Sigma//spl Delta/ modulator implementation with respect to a minimal power consumption on the one hand and to fulfil a rapid prototyping approach on the other hand. This method compares the power efficiency of different modulator structures and modulator orders with respect to the given design specifications. The efficiency of this strategy is shown by measurement results of a 1.5V 3/sup rd/ order CT modulator.

A 16-port FCC-compliant 10GBase-T transmitter and hybrid with 76dBc SFDR up to 400MHz scalable to 48 ports

High-density 48-port network switches demand very power-efficient, small form-factor quad PHYs which comply with the IEEE 802.3an transmit PSD and return-loss requirements on the one hand and meet the FCC Class-A specifications on the other hand. We present a 10GBase-T transmitter and hybrid that uses a highly correlated current-mirroring amplifier with output rise time control and high CMRR to perform a first-order linear and non-linear echo cancellation while enabling the design of 48-port FCC compliant network switches. Experimental results over the 400MHz bandwidth exhibit a transmitter linearity of >;57dBc as well as a residual linear echo and distortion of -28dBc and 76dBc, respectively. Implemented in a 40nm CMOS technology, the transmitter plus hybrid consumes 200mW power and occupies 0.5mm2.