Lowell H. Miles

An 860-Mb/s (8158,7136) Low-Density Parity-Check Encoder

Low-density parity-check codes achieve coding performance which approaches the Shannon limit. An (8158,7136) encoder was implemented in a five-metal, 0.25-mum CMOS process. Use of generator polynomial reconstruction, partial product multiplication and functional sharing in the parity register results in a highly efficient design. Only 1492 flip-flops along with a programmable 21-bit look-ahead scheme are used to achieve an 860-Mb/s data throughput for this rate 7/8 LDPC code. A comparable two-stage encoder requires 8176 flip-flops

An ultra-low-power, radiation-tolerant Reed Solomon encoder for space applications

Power is a limiting constraint in spacecraft design. This paper describes a Reed Solomon encoder designed for NASA using a triple metal, 0.35 /spl mu/m, ultra-low-power (500mV) CMOS process. Comparisons with a 3.3 V version show a 29.6 to 1 reduction in power to 14.3 mW at 60 MHz. Hardness against space radiation effects was achieved through circuit and layout techniques.

An (8158,7136) low-density parity-check encoder

Low-density parity-check codes achieve coding performance which approaches the Shannon limit. Based on a novel method for deriving regular quasi-cyclic sub-codes, a radiation tolerant encoder was implemented in 0.25/spl mu/m CMOS. Use of generator polynomial reconstruction, partial product multiplication and functional sharing in the parity register results in a highly efficient design. Only 1,492 flip flops along with a programmable 21-bit look-ahead scheme are used to achieve a 1 Gb/s data throughput. A comparable two-stage encoder requires 8,176 flip flops.

Heavy ion test results of RHBD standard cells and memory in a 110nm bulk CMOS process

This paper describes heavy ion testing and results gathered from a test chip produced in the ON Semiconductor 110nm process. Content on this test chip includes conventional CMOS standard cells augmented with Radiation Hardened By Design (RHBD) library elements and dual port SRAM with error correction code (ECC) developed specifically for SEE concerns and high performance operation. Favorable test results are presented showing SEE performance of the Self Restoring Logic (SRL) cell to 140 MeVcm2/mg onset LET for upsets. Additionally, SRL based polynomial counters performed flawlessly at 700MHz to an LET of 78 MeVcm2/mg. SEL protection of the bulk CMOS process using the special support cells is described. SRL flip flop results are compared to legacy DICE and SERT flip flop architecture results.

Radiation Tolerance Techniques for a 1.6 Gb/s, 8 K and 4 K Low-Density Parity-Check Encoder

A multiple node upset tolerant, 1.6 Gb/s (8158, 7136) and (4088, 3360) low-density parity-check encoder was implemented in a five-metal, 0.25 mum CMOS process. Temporal separation coupled with single-event radiation tolerant flip-flops was used to harden the data path. A reduced sensitive cross-section combinational logic structure was used to harden the custom multiply accumulate blocks. This circuit structure is composed of a dual-rail NMOS-only pass-transistor network driving a cross coupled output buffer. By adding the output buffer section, only a small region of the buffer itself is vulnerable for propagation of a single-event transient. Single-event upset immunity with a linear energy transfer threshold of greater than 33 MeVldrcm2/mg and a saturation cross-section of just 0.075 mum2/bit was achieved for the 4 K encoder. A linear energy transfer threshold of greater than 17 MeVldrcm2/mg with a saturation cross-section of just 0.3 mu m2/bit was achieved for the 8 K encoder. This results in a CREME96 expected mean time between failure of 1700 years for a geosynchronous orbit. Multiple node upsets as a problem increases as smaller geometry processes are used for space electronics. A mathematical basis for this reduced cross-section, multiple upset combinational logic design method is presented.