Luca Corradini

High-Bandwidth Multisampled Digitally Controlled DC–DC Converters Using Ripple Compensation

This paper investigates multi sampled digitally controlled switched-mode power supplies with switching ripple compensation. In digital controllers for power converters, the main bandwidth limitations come from A/D conversion time, computational delays, and small-signal delay of the digital pulsewidth modulator (DPWM). In hard-wired digital-controller technologies, such as in dedicated digital IC and/or in field-programmable gate arrays (FPGAs), the calculation delays can be made negligible with respect to the switching period; thus, when fast ADCs are used, the overall phase lag is dominated by the DPWM. The multi sampling approach can strongly reduce the DPWM delay, thus breaking the bandwidth limitations of conventional single-sampled solutions. In this paper, the additional aliasing effects, which would require a filtering action, are avoided, exploiting the periodic nature of the switching ripple under steady-state conditions using a repetitive-based filtering action. Simulation and experimental results on a 1.2-V-10-A 500-kHz synchronous buck converter, where the digital control has been implemented in the FPGA, confirm the properties of the proposed solution.

Minimum Current Operation of Bidirectional Dual-Bridge Series Resonant DC/DC Converters

This paper discusses the steady-state operation of phase-shift modulated dual-bridge series resonant converter (DBSRC) intended for dc/dc power bidirectional control over a wide range of input and output voltages. The analysis, developed here for the most general case of three independent phase-shift control angles, demonstrates the existence of minimum current trajectories in the 3-D control space along which the DBSRC cell can deliver any admissible power level with minimum tank circulating current. At nonunity conversion ratios, minimum current operation prevents the DBSRC output bridge from experiencing severe hard-switching losses, substantially reducing the effort normally required by auxiliary zero-voltage switching assistance circuitry, and outperforming the efficiency of conventional one-angle modulation approaches especially at light load. The developed approach is validated via computer simulations and experimental tests on a 1-kW DBSRC prototype. Tests performed at a nonunity voltage conversion ratio indicate a marked light-load efficiency improvement with respect to the conventional one-angle modulation, confirming the importance of the minimum current operation when the converter is expected to operate with programmable output voltages or under wide input voltage variations.

Parameter-Independent Time-Optimal Digital Control for Point-of-Load Converters

In this paper, a digital control approach is investigated for time-optimal load step response of DC-DC synchronous buck converters intended for point-of-load (PoL) applications and employing low-equivalent series resistance ceramic output capacitors. Unlike previously reported approaches, the proposed technique is insensitive to converter parametric variations and design uncertainties, as its operation does not rely on the knowledge of the output filter inductance or capacitance. The time-optimal response is achieved through a single on/off switching action undertaken as soon as a load transient is detected. In its most general formulation, the proposed technique automatically incorporates adaptive voltage positioning (AVP) regulation, according to the typical droop design guidelines for powering modern microprocessors. A simpler version, suitable for voltage-mode controlled PoL converters not requiring AVP positioning, is also presented. The technique employs an asynchronous A/D conversion scheme, which quantizes the converter state variables and triggers a nonlinear, event-based digital controller whenever a quantization level transition is detected. Additional sensing requirements are not needed, since the time-optimal transient is achieved through the measurement of the output voltage and, whenever AVP regulation is needed, of the phase currents. Effectiveness and properties of the proposed robust time-optimal approach are validated through both computer simulations and experimental tests on a synchronous buck converter prototype and a VHDL implementation of the control algorithm on an field programmable gate array device.

Time optimal, parameters-insensitive digital controller for DC-DC buck converters

In this paper a digital control approach is investigated for time-optimal load step response of DC-DC synchronous buck converters intended for point-of-load applications employing low-ESR ceramic output capacitors. Unlike previously reported approaches, the proposed technique is insensitive to the power stage parameters, as its operation does not rely on the knowledge of the output filter inductance or capacitance. The time-optimal response is achieved through a single on/off switching action undertaken as soon as a load transient is detected. An asynchronous A/D converter has been employed, realized in a standard 0.35 mum CMOS process. The A/D converter quantizes the output voltage and triggers a nonlinear, event-based digital controller whenever a quantization level transition is detected. Time-optimal response is based solely on output voltage measurements and on the knowledge of the steady-state duty cycle, a number easily available within the digital controller. Effectiveness and properties of the proposed robust time-optimal approach are validated through both computer simulations and experimental tests on a synchronous buck converter prototype and a VHDL implementation of the control algorithm on an FPGA device.

Modeling of Multisampled Pulse Width Modulators for Digitally Controlled DC–DC Converters

This paper presents steady-state and small-signal models for digital pulsewidth modulators (DPWM) employed in multiple sampling digital control schemes for dc-dc switched mode power supplies (SMPS), and identifies the triangular modulation as intrinsically superior to other modulation schemes in multisampling applications. In conventional digital control of dc-dc converters, closed-loop bandwidth limitations are mainly set by analog-to-digital conversion times, computational delays and DPWM delays originated by the sampled nature of the PWM. While the use of hardwired logic and fast A/D converters minimizes computational and A/D delays, the DPWM small-signal phase lag strictly depends on the adopted sampling strategy. Multiple sampling techniques recently proposed in literature can achieve a strong reduction of the DPWM delay by operating the control and modulation steps at a sampling frequency strictly higher than the converter switching frequency. On the other hand, multisampled pulse width modulators (MSPWMs) exhibit nonlinear behaviors which do not have analog counterparts nor are encountered in conventional digital control, the most relevant effect being the onset of sampling induced dead bands, i.e., regions of zero modulation gain in the modulator transcharacteristic which may compromise proper closed-loop operation of the converter. The models proposed in this paper fully characterize the steady-state and small-signal behavior of DPWMs operated in multiple-sampling fashion. Multisampled triangular modulators are proven to be intrinsically superior to trailing edge or leading edge modulators in terms of linearity. Simulation and experimental results validate the proposed models and confirm the properties of triangular modulations.

Analysis of Parallel Operation of Uninterruptible Power Supplies Loaded Through Long Wiring Cables

This paper discusses and analyses the parallel operation of uninterruptible power supplies (UPS) when loaded through long wiring cables having non-negligible inductance and resistance. This scenario is often encountered in practice, as the UPS power supplies are often located far from each other and from the load they are actually powering. The analysis demonstrates how long cable connections between the power supply system and the load deeply modify the behavior of the single UPS unit. It is shown how the cable inductance interacts with the UPS closed-loop output impedance modifying the control loop gain, ultimately generating resonance phenomena, which deteriorate or even compromise system stability and performances, if suitable provisions are not taken at the design stage. Experimental results carried out on two paralleled three phase, 40 kVA UPS units based on voltage-source inverters topologies confirm the validity of the theoretical discussion and the practical relevance of the phenomenon.

Autotuning Techniques for Digitally-Controlled Point-of-Load Converters with Wide Range of Capacitive Loads

This paper addresses auto-tuning of digital controllers for point-of-load (POL) switching converters with wide range of capacitive loads. Two auto-tuning methods are considered with particular attention given to robustness and feasibility. The first method is derived from the well known relay-feedback autotuning technique, where specific frequencies are excited to gain information on the power stage. In the second, system-identification based method, compensator parameters are computed based on on-line identification of the power stage frequency response. The tuning techniques proposed in this paper have been specifically developed to handle wide capacitance and ESR range, and important extensions of the basic algorithms are implemented in order to face practical issues such as limit cycling conditions, output voltage tolerance specification, closed-loop bandwidth maximization and phase margin constraints. Simulation and experimental results on a 12-to-1.5 V, 9 A, 200 kHz POL converter are provided to show the effectiveness and to compare the considered techniques.

Simplified Model Reference-Based Autotuningfor Digitally Controlled SMPS

This paper presents a closed-loop self-tuning technique for digitally controlled dc-dc switched-mode power supplies (SMPS) based on proportional-integral-derivative (PID) regulators, which derives from the more general model reference autotuning techniques. After briefly discussing an open loop, model-reference based tuning technique, a closed-loop solution is presented in which a perturbation frequency generated digitally is injected into the control loop and superimposed to the duty cycle command. The tuning is performed elaborating the signals right before and right after the injection point, and adjusting the PID parameters until predefined bandwidth and phase margin targets are obtained. The proposed approach allows for a robust and repeatable tuning, mainly because of the high resolution and dynamics available at the signal injection point. Moreover, the tuning is performed maintaining the closed-loop configuration, thus ensuring voltage regulation even during the PID adjustment, this being a fundamental constraint for most electronic equipments. The proposed technique is simple from the signal processing point of view, since it requires a few integrations, multiplications and phase-shift; further simplified implementations by employing nonsinusoidal perturbation waveforms like square-wave or triangular signals are also proposed. The approach is first discussed for two-parameters PI and PD regulators, and successively extended to PID structures, for which two possible implementations are proposed. The effectiveness of the tuning approach is verified by means of computer simulations and experimental tests carried out on a digital signal processor platform interfaced with a prototype point-of-load converter. The complexity of an HDL-implementation of the tuning hardware for field programmable gate array platforms is also discussed.

Adaptive Tuning of Switched-Mode Power Supplies Operating in Discontinuous and Continuous Conduction Modes

This paper presents an approach to adaptive tuning of voltage-mode digital controllers for switched-mode power supplies in the presence of large signal changes from discontinuous conduction mode (DCM) to continuous conduction mode (CCM) and vice versa. The approach is capable of maintaining a high-performance control loop without the stability issues related to DCM-to-CCM mode transitions. The adaptive tuner, modeled as a multiple-input-multiple-output (MIMO) controller, is designed to continuously adjust the parameters of a PID compensator such that crossover frequency and phase margin measured by the digital controller match desired values. A simplified design procedure for the adaptive tuning system is proposed that reduces the small-signal MIMO design into two independent single-input, single-output control loops. Simulation results are given showing that despite wide uncertainty in the power stage, the adaptive tuning system still converges to the desired stability margins. Experimental results are given using an 11- to 5-V, 45-W, DCM/CCM buck converter as a test bed.

Analysis of Multi-Sampled Current Control for Active Filters

This paper investigates the multisampling techniques applied to the current control in active-power-filter (APF) applications. In APF applications with digital control, the main bandwidth limitation derives from A/D conversion and computational delays and the sampling-related delay of the digital pulsewidth modulation (DPWM). Using field-programmable gate arrays and fast A/D converters for the control implementation, it is possible to minimize the former two; thus, the overall phase lag is dominated by the DPWM, which can strongly be reduced by the multiple-sampling approach, breaking bandwidth limitations of single-sampled solutions. Moreover, as the multisampling approach triggers nonlinear behaviors that can negatively impact the filter-compensating capabilities, a solution based on a simple digital filter is proposed which linearizes the system behavior and does not waste the multisampling advantages. Simulation and experimental results on a 10-kVA prototype confirm the theoretical expectations.