Stefano Saggini

An innovative digital control architecture for low-Voltage, high-current DC-DC converters with tight voltage regulation

This paper describes an innovative digital control architecture for low-voltage, high-current dc-dc converters, based on a combination of current-programmed control and variable frequency operation. The key feature of the proposed architecture is the low complexity: only two digital-to-analog converters (DACs) with low resolution (7-b) are used for control. An original control algorithm is used to reduce quantization effects to negligible levels, in spite of the low resolution of the DACs. Thanks to this algorithm, both static and dynamic output voltage regulation are improved with respect to traditional digital solutions. Adaptive voltage positioning and active current sharing are inherently provided by the new architecture. A detailed description of the control strategy is given with reference to a single-phase buck converter. Extension to multiphase converters is straightforward. The digital control architecture is experimentally verified on a FPGA-based four-phase prototype buck converter operating at 350 kHz/phase. Output voltage tolerance within /spl plusmn/0.5% is experimentally demonstrated, along with negligible quantization effects and fast transient response. The features and the performance of the proposed architecture make it a valuable candidate for the control of next generation voltage regulator modules.

Autotuning of Digitally Controlled DC–DC Converters Based on Relay Feedback

This paper proposes a simple autotuning technique for digitally controlled dc-dc converters. The proposed approach is based on the relay feedback method and introduces perturbations on the output voltage during converter soft-start. By using an iterative procedure, the tuning of proportional-integral-derivative parameters is obtained directly by including the controller in the relay feedback and by adjusting the controller parameters based on the specified phase margin and control loop bandwidth. A nice property of the proposed solution is that output voltage perturbations are introduced while maintaining the relay feedback control on the output voltage. The proposed algorithm is simple, requires small tuning times, and it is compliant with the cost/complexity constraints of integrated digital integrated circuits. Simulation and experimental results of a synchronous buck converter and of a dc-dc boost converter confirm the effectiveness of the proposed solution

Li-Ion Battery-Supercapacitor Hybrid Storage System for a Long Lifetime, Photovoltaic-Based Wireless Sensor Network

This paper proposes a power management architecture that utilizes both supercapacitor cells and a lithium battery as energy storages for a photovoltaic (PV)-based wireless sensor network. The supercapacitor guarantees a longer lifetime in terms of charge cycles and has a large range of operating temperatures, but has the drawback of having low energy density and high cost. The lithium battery has higher energy density but requires an accurate charge profile to increase its lifetime, feature that cannot be easily obtained supplying the wireless node with a fluctuating source as the PV one. Combining the two storages is possible to obtain good compromise in terms of energy density. A statistic analysis is used for sizing the storages and experimental results with a 5-W PV energy source are reported.

Autotuning of Digitally Controlled Buck Converters Based on Relay Feedback

This paper proposes a simple autotuning technique for digitally controlled dc-dc synchronous buck converters. The proposed approach is based on the relay feedback method and introduces perturbations on the output voltage during converter soft-start. By using an iterative procedure, the tuning of PID parameters is obtained directly by including the controller in the relay feedback and by adjusting the controller parameters based on the specified phase margin and control loop bandwidth. A nice property of the proposed solution is that output voltage perturbations are introduced while maintaining the closed-loop control of the digitally controlled converters. The proposed algorithm is simple, requires small tuning times and it is compliant with the cost/complexity constraint of integrated digital ICs. Experimental investigation has been performed using discrete components, implementing the digital control in a field programmable gate array (FPGA). Simulation and experimental results of a 1.5 V-5 A synchronous buck converter confirm the effectiveness of the proposed solution

Parameter-Independent Time-Optimal Digital Control for Point-of-Load Converters

In this paper, a digital control approach is investigated for time-optimal load step response of DC-DC synchronous buck converters intended for point-of-load (PoL) applications and employing low-equivalent series resistance ceramic output capacitors. Unlike previously reported approaches, the proposed technique is insensitive to converter parametric variations and design uncertainties, as its operation does not rely on the knowledge of the output filter inductance or capacitance. The time-optimal response is achieved through a single on/off switching action undertaken as soon as a load transient is detected. In its most general formulation, the proposed technique automatically incorporates adaptive voltage positioning (AVP) regulation, according to the typical droop design guidelines for powering modern microprocessors. A simpler version, suitable for voltage-mode controlled PoL converters not requiring AVP positioning, is also presented. The technique employs an asynchronous A/D conversion scheme, which quantizes the converter state variables and triggers a nonlinear, event-based digital controller whenever a quantization level transition is detected. Additional sensing requirements are not needed, since the time-optimal transient is achieved through the measurement of the output voltage and, whenever AVP regulation is needed, of the phase currents. Effectiveness and properties of the proposed robust time-optimal approach are validated through both computer simulations and experimental tests on a synchronous buck converter prototype and a VHDL implementation of the control algorithm on an field programmable gate array device.

Time optimal, parameters-insensitive digital controller for DC-DC buck converters

In this paper a digital control approach is investigated for time-optimal load step response of DC-DC synchronous buck converters intended for point-of-load applications employing low-ESR ceramic output capacitors. Unlike previously reported approaches, the proposed technique is insensitive to the power stage parameters, as its operation does not rely on the knowledge of the output filter inductance or capacitance. The time-optimal response is achieved through a single on/off switching action undertaken as soon as a load transient is detected. An asynchronous A/D converter has been employed, realized in a standard 0.35 mum CMOS process. The A/D converter quantizes the output voltage and triggers a nonlinear, event-based digital controller whenever a quantization level transition is detected. Time-optimal response is based solely on output voltage measurements and on the knowledge of the steady-state duty cycle, a number easily available within the digital controller. Effectiveness and properties of the proposed robust time-optimal approach are validated through both computer simulations and experimental tests on a synchronous buck converter prototype and a VHDL implementation of the control algorithm on an FPGA device.

Digital Deadbeat Control Tuning for dc-dc Converters Using Error Correlation

This letter proposes a simple tuning algorithm for digital deadbeat control based on error correlation. By injecting a square-wave reference input and calculating the correlation of the control error, a gain correction for deadbeat control is obtained. The proposed solution is simple, it requires a short tuning time, and it is suitable for different DC-DC converter topologies. Simulation and experimental results on synchronous buck converters confirm the properties of the proposed tuning algorithm.

Simplified Model Reference-Based Autotuningfor Digitally Controlled SMPS

This paper presents a closed-loop self-tuning technique for digitally controlled dc-dc switched-mode power supplies (SMPS) based on proportional-integral-derivative (PID) regulators, which derives from the more general model reference autotuning techniques. After briefly discussing an open loop, model-reference based tuning technique, a closed-loop solution is presented in which a perturbation frequency generated digitally is injected into the control loop and superimposed to the duty cycle command. The tuning is performed elaborating the signals right before and right after the injection point, and adjusting the PID parameters until predefined bandwidth and phase margin targets are obtained. The proposed approach allows for a robust and repeatable tuning, mainly because of the high resolution and dynamics available at the signal injection point. Moreover, the tuning is performed maintaining the closed-loop configuration, thus ensuring voltage regulation even during the PID adjustment, this being a fundamental constraint for most electronic equipments. The proposed technique is simple from the signal processing point of view, since it requires a few integrations, multiplications and phase-shift; further simplified implementations by employing nonsinusoidal perturbation waveforms like square-wave or triangular signals are also proposed. The approach is first discussed for two-parameters PI and PD regulators, and successively extended to PID structures, for which two possible implementations are proposed. The effectiveness of the tuning approach is verified by means of computer simulations and experimental tests carried out on a digital signal processor platform interfaced with a prototype point-of-load converter. The complexity of an HDL-implementation of the tuning hardware for field programmable gate array platforms is also discussed.

Digital Time-Optimal Phase Shedding in Multiphase Buck Converters

This letter proposes a time-optimal digital controller for the phase shedding (PS) in multiphase buck converters. PS is an established technique to improve the efficiency of multiphase converters at light load by changing the active number of phases depending on the load-current level. In order to minimize the output-voltage deviation and the transient time during PS, a minimum time algorithm is investigated. The proposed technique is insensitive to the power stage parameters, as its operation relies only on a feedforward action, depending on the steady-state duty cycle and the number of phases to be turned on or turned off. The proposed approach is validated through experimental tests on a synchronous buck converter.

Power Line Communication in Digitally Controlled DC–DC Converters Using Switching Frequency Modulation

This paper investigates power line communication (PLC) in digitally controlled high-frequency switched-mode power supplies in distributed architectures that share the same bus voltage. Communication between different DC-DC converters is obtained by using switching frequency modulation and by detecting the switching signal on the common supply bus voltage. In case of low power transmission, a small duty-cycle perturbation at half of switching frequency is added to enhance the energy of the transmitted signal. Each converter operates at three different switching frequencies: the first is associated with bit 1 transmission, the second is associated with bit 0 transmission, and the third is associated with no transmission state. In the proposed solution, there is no need for an additional power amplifier in order to inject the communication signal on the power lines, but the signal used for the PLC is inherently generated by the pulsewidth modulation of DC-DC converters. Even if aimed at a dedicated digital IC, the communication architecture has been implemented in field-programmable gate arrays. Simulation and experimental results on DC-DC synchronous buck converters confirm that the performance is achievable by the proposed PLC techniques.