Luca Ravezzi

Single-ended transceiver design techniques for 5.33Gb/s graphics applications

Graphics processing is the driving force behind the demand for high-bandwidth DRAMs. Accelerating the pace of bandwidth improvement, fifth-generation graphics DDRs will operate at data rates up to 5.33Gb/s, and support single-ended signaling for low pin-count. A significant design challenge is to ensure proper signal transmission over single-ended wires at rates previously attainable only with differential pairs. We present single-ended transceiver design techniques for 5.33Gb/s operation. In addition to the receiver and transmitter, a CML-to-CMOS converter and an integrated serializer/level-shifter are described (Fig. 7.5.1). The circuits are fabricated in 0.13µm 1.2V CMOS. The chip area is 5.7×7.0mm2 and is housed in a quadratic BGA package with 289 balls.

5.8 A 3GHz 64b ARM v8 processor in 40nm bulk CMOS technology

Potenza is a first generation 64b ARM v8 processor and memory sub-system of the X-GeneTM server platform [1]. The Potenza processor module (PMD) is an integrated design unit, comprising two identical cores sharing a 256KB L2 cache, and is designed to be scalable for different server configurations. Each PMD contains 84 million transistors, occupying over 14.8mm2, and averages 4.5W under representative workloads. The initial platform is configured with 4 PMDs, a shared 8MB L3 cache, and 4 DRAM channels arranged around a central switch. Potenza can operate up to 3GHz at 0.9V supply and is fabricated in a 40nm bulk CMOS technology using 10 metal layers (Fig. 5.8.7).

Clock and Synchronization Networks for a 3 GHz 64 Bit ARMv8 8-Core SoC

This paper describes the clock distribution and synchronization network for a 64 bit ARMv8 8-core microprocessor. Embedded in a SoC for cloud computing platforms, the processor is fabricated in a 40 nm CMOS technology and operates at 3.0 GHz. The system PLL has a measured rms jitter <;1 ps and features dynamic frequency hopping for DVFS applications. In conjunction with a Star/H/Mesh topology, the clock distribution uses both CML and CMOS circuits to minimize period jitter and nominally achieves <;0.8 ps/mV | rms and <;9 ps of period jitter and skew, respectively. By using local Duty Cycle Adjustment circuits in each core to properly offset the clock duty cycle and ease timing critical paths, the processor performance improves by more than 5%. A simple probing circuit for high speed clock measurements can be used to monitor the high frequency excursions of the internal supply to counteract any timing violation that could occur. Finally an enhanced latch, which improves MTBF by up to 5 orders of magnitude and thus is suited for high speed synchronization operations, is proposed.

A 3-stage Pseudo Single-phase Flip-flop family

This paper presents an energy-efficient 3-stage Pseudo Single-phase family of Flip-flops (PSPFF) targeted for use in a 3GHz microprocessor in a 40nm, 0.9V CMOS technology. With latencies in line with the fast pulsed-latch and an average switching energy comparable to the master-slave flip-flop, PSPFF achieves an energy-delay product (EDP) which is 42% and 24% lower than the pulsed-latch and the master-slave flip-flop respectively. Measurement results confirm an improvement of at least 300MHz in operating frequency when using the PSPFF in place of the master-slave flip-flop.