Karthik Gopalakrishnan

Single-ended transceiver design techniques for 5.33Gb/s graphics applications

Graphics processing is the driving force behind the demand for high-bandwidth DRAMs. Accelerating the pace of bandwidth improvement, fifth-generation graphics DDRs will operate at data rates up to 5.33Gb/s, and support single-ended signaling for low pin-count. A significant design challenge is to ensure proper signal transmission over single-ended wires at rates previously attainable only with differential pairs. We present single-ended transceiver design techniques for 5.33Gb/s operation. In addition to the receiver and transmitter, a CML-to-CMOS converter and an integrated serializer/level-shifter are described (Fig. 7.5.1). The circuits are fabricated in 0.13µm 1.2V CMOS. The chip area is 5.7×7.0mm2 and is housed in a quadratic BGA package with 289 balls.

A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications

A key challenge in optical networking is the development of low-power transceivers that interface to optical sub-assemblies (TOSAs & ROSAs). While SiGe technologies are often selected for jitter performance with optical links, especially on the egress path to the transmit optics, lower-power and higher levels of digital integration often result from CMOS approaches . This paper describes a generic CMOS 25-to-30Gb/s SerDes for use within CDR or gearbox applications, targeting the draft requirements of the OIF 28G-VSR standard and suitable for both 100GBASE-LR4/OTL4.4 gearbox and retiming applications, including CFP and CFP2.

3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS

High-speed signaling using NRZ has approached speeds above 50Gb/s where it is extremely difficult to maintain power efficiency and performance over a wide variety of channels and applications. PAM-4 is emerging as one way to increase throughput in such band-limited channels. Higher modulation formats help to address cost in optical systems by packing more bits/wavelength [1]. Strong momentum in standards to adopt PAM-4 reflects these significant trends in the industry. At the same time, migrating transceiver designs to current technology nodes have narrowed the power gap between traditional Analog and ADC-DSP-DAC-based systems for high-speed applications. These factors make ADC-based receivers a highly desirable choice, as is also the trend in wireless communications.

A background calibrated 28GS/s 8b interleaved SAR ADC in 28nm CMOS

A 28-GS/s time-interleaved ADC suitable for PAM4 optical and backplane applications is presented. The architecture uses a two-rank 2×(4:4) sampling network to interleave 32 8b SAR ADCs employing redundancy to relax DAC settling requirements. A DSP core estimates and corrects the gain, offset and timing error between channels. An ENOB of 5.8b and 5.4b is achieved with 1-GHz and 13.3GHz input signals. The ADC consumes 165-mW from a single 950-mV power supply and is fabricated in a 28nm CMOS process occupying 0.24mm2.