Lucian Prodan

Biology Meets Electronics: The Path to a Bio-inspired FPGA

Embryonics (embryonic electronics) is a research project that attempts to draw inspiration form the world of biology to design better digital computing machines, and notably massively parallel arrays of processors. In the course of the development of our project, we have realized that the use of programmable logic circuits (field-programmable gate arrays, or FPGAs) is, if not indispensable, at least extremely useful. This article describes some of the peculiar features of the FPGA we designed to efficiently implement our embryonic machines. More particularly, we discuss the issues of memory storage and of self-repair, critical concerns for the implementation of our bio-inspired machines.

Self-repairing embryonic memory arrays

Space applications endorse the quest for dependable computing as a vital requirement instead of an expendable quality indicator. A novel direction in designing digital systems with superior dependability is based on bio-inspiration. As a key representative, the Embryonics project implements bio-inspired robustness, the backbone of its fault tolerance being a two level hierachical self-repair. However, the outer space radiation-hard environment is especially harsh to electronic devices, causing a variety of errors (soft fails). The memory structures employed by Embryonics cannot be protected by its self-repairing mechanism. Therefore we investigate the causes and influences of soft fails over the current Embryonics framework and propose a solution for the identified vulnerability based on error correcting codes. We also provide a reliability comparison between memory structures with and without error correcting codes.

Embryonics: Artificial Cells Driven by Artificial DNA

Embryonics is a long-term research project attempting to draw inspiration from the biological process of ontogeny, to implement novel digital computing machines endowed with better fault-tolerant capabilities. For this purpose FPGAs are extremely useful. However, throngh this project we designed MuxTree, a new coarse-grained FPGA, to implement our embryonic machines. This article focuses on the issues posed by the memory storage and the advances made to achieve more robust memory structures.

Implementing quantum genetic algorithms: a solution based on Grover's algorithm

This paper presents a new methodology for running Genetic Algorithms on a Quantum Computer. To the best of our knowledge and according to reference [6]there are no feasible solutions for the implementation of the Quantum Genetic Algorithms (QGAs). We present a new perspective on how to build the corresponding QGA architecture. It turns out that the genetic strategy is not particularly helpful in our quantum computation approach; therefore our solution consists of designing a special-purpose oracle that will work with a modified version of an already known algorithm (maximum finding [1]), in order to reduce the QGAs to a Grover search. Quantum computation offers incentives for this approach, due to the fact that the qubit representation of the chromosome can encode the entire population as a superposition of basis-state values.

Improving quantum circuit dependability with reconfigurable quantum gate arrays

The need for error detection and correction techniques is vital in quantum computation, due to the omnipresent nature of quantum errors. No realistic prospect of an operational quantum computational device may be warranted without such mechanisms. Therefore, the fact that error detecting and correcting techniques have been developed has enhanced the feasibility of a potential quantum computer [15] [18]. This paper presents a methodology for improving the fault tolerance of quantum circuits by using the so-called reconfigurable Quantum Gate Arrays (rQGAs). Our solution reduces the problem of stabilizer coding safe recovery to preserving a given quantum configuration state. As shown in this papers practical example, the configuration register to be protected has a reduced number of qubits, and the overall dependability attribute [2]-- reliability measured by the accuracy threshold [15]-- is drastically improved

The Bubble Bit Technique as Improvement of HDL-Based Quantum Circuits Simulation

When performed on a classical computer, the simulation of quantum circuits is usually an exponential job. The methodology based on Hardware Description Languages is able to isolate the entanglement as source of simulation complexity. However, it was shown that this methodology is not efficient in the presence of total entanglement, and the probability of such a situation grows exponentially with the number of qubits [ M. Udrescu, L. Prodan, M Vladutiu (2004) ]. The bubble bit technique is designed to avoid the entangled representation of the quantum state, thus allowing the HDL structural description of the quantum circuit, which requires polynomial resources for simulation. We provide experimental runtimes, obtained by simulation of quantum arithmetic and Grovers algorithm circuits, which indicate substantial runtime speedup.

Secret data communication system using steganography, AES and RSA

The paper introduces a new secret data communication system that employs the usage of two state-of-the art cryptographic algorithms (RSA with asymmetric keys and AES with symmetric key) together with steganography. The joining of these three techniques builds a robust steganography-based communication system capable of withstanding multiple types of attacks, detection and reverse engineering. Our system was designed in a way that offers a solution to the major flaws presented in other steganographic communication systems [2][4][5][6]. The secret data is encrypted using AES with a strong key prior to being embedded using a steganographic algorithm [1]. The key used for the data encryption uses a combination between a random generated sequence and a hash of the cover images color information that remains untouched throughout the entire embedding process. The secret data and the key used for encryption both pass multiple levels of security checks that assure the integrity, authenticity and security, making this a reliable communication channel for sensitive data. While all encryption stages assure that the secret data becomes obsolete without the proper decryption perquisites (keys), the steganographic algorithm introduces an additional level of security: stealth.

Automatic Synthesis for Quantum Circuits Using Genetic Algorithms

This paper proposes an automated quantum circuit synthesis approach, using a genetic algorithm. We consider the circuit as a successive rippling of the so-called gate sections; also, the usage of a database is proposed in order to specify the gates that will be used in the synthesis process. Details are presented for an appropriate comparison with previous approaches, along with experimental results that prove the convergence and the effectiveness of the algorithm.

Decreasing Change Impact Using Smart LSB Pixel Mapping and Data Rearrangement

The paper introduces a new optimization strategy in LSB steganography that reduces the image degradation rate in the steganographic carrier. We propose an LSB matching steganographic algorithm based on the principles of genetic algorithms, that aims to reuse the binary image color values in a controlled way so that instead of focusing to change the least significant portion of the color representation (LSBs), we remap the secret data in a manner that reduces the color information loss up to a negligible level. The algorithm improves the statistical analysis immunity of the steganographic image and at the same time offers higher PSNR (an average gain of 2,4 dB) than most of the LSB matching algorithms used in our experiments. Because of the flexibility of this approach, our method represents not only a stand-alone steganographic algorithm, but also an extension to other similar algorithms.

Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor

This paper proposes a new approach for the optimization process of the interval addition and multiplication floating point units. For the interval addition/subtraction, an adder exploiting the parallelism of the double path adder structure is used. The two floating point additions needed are performed simultaneously on different data paths. Therefore, the performance of the proposed adder can be the same as that of two individual floating point adders, but with a much reduced cost overhead. Regarding the interval multiplication, a multiplier architecture was designed, in order to be suitable for pipelined structures. It consists of a floating point multiplier which computes two results for the same operation (rounded differently), and of two floating point comparators. In terms of performance, the proposed multiplier unit presents half of the performance of a conventional floating point multiplier. This is not a drawback, if we consider the fact that interval multiplication requires four floating point operations and six comparisons. This paper shows that interval arithmetic can be efficiently implemented in terms of performance and cost.