Luigi Colalongo

Electron and hole mobility in silicon at large operating temperatures. I. Bulk mobility

In this paper, an experimental investigation on high-temperature carrier mobility in bulk silicon is carried out with the aim of improving our qualitative and quantitative understanding of carrier transport under ESD events. Circular van der Pauw patterns, suitable for resistivity and Hall measurements, were designed and manufactured using both the n and p layers made available by the BCD-3 smart-power technology. The previous measurements were carried out using a special measurement setup that allows operating temperatures in excess of 400/spl deg/C to be reached within the polar expansions of a commercial magnet. A novel extraction methodology that allows for the determination of the Hall factor and drift mobility against impurity concentration and lattice temperature has been developed. Also, a compact mobility model suitable for implementation in device simulators is worked out and implemented in the DESSIS/spl copy/ code. Comparisons with the mobility models by G. Masetti et al. (1983) and D.B.M. Klaassen (1992) are shown in the temperature range between 25 and 400/spl deg/C.

A 0.2

In this paper, a dc/dc converter is presented that can boost very low voltages to the typical supply voltages of current integrated circuits (1.2 V-1.5 V). The converter is based on a new hybrid inductive and capacitive architecture and it is suitable for power harvesting applications too. The measured prototype can supply 1.2 V by converting an input voltage of 200 mV delivered by a thermopile exposed to a 5degC thermal gradient. A chip was designed and fabricated using a United Microelectronics Corp. (UMC) 180-nm low-threshold CMOS process. Measurements on the chip confirm the validity of the design.

-\hbox{1.2}

Thin-film transistors (TFTs), which use zinc oxide (ZnO) as an active layer, were fabricated and investigated in detail. The transport properties of ZnO deposited by spray pyrolysis (SP) on a TFT structure are studied in a wide range of temperatures, electrical conditions (i.e., subthreshold, above-threshold linear, and saturation regions), and at different channel lengths. It is shown that ZnO deposited by SP is a nanocrystalline material; its field-effect mobility is temperature activated and increases with carrier concentration. On the basis of this analysis, we propose the multiple-trapping-and-release (MTR)-transport mechanism to describe the charge transport in ZnO. By means of numerical simulations, we prove that MTR is a suitable approach, and we calculate the density of states. We show that the tail states extend in a wide range of energy and that they strongly influence the transport properties. Finally, an analytical physical-based DC model is proposed and validated with experiments and numerical simulations. The model is able to reproduce the measurements on devices with different channel length in a wide range of bias voltages and temperatures by means of a restricted number of parameters, which are linked directly to the physical properties of the ZnO semiconductor. For the first time, the charge transport in the ZnO is investigated by means of the MTR, and a consistent analysis based on experiments, numerical simulations, and analytical modeling is provided.

V DC/DC Boost Converter for Power Harvesting Applications

To the authors knowledge, this is the first time that a paper demonstrates the feasibility of a fully integrated step-up converter based on inductive elements. The prototype is fabricated in the ST M8 0.18-/spl mu/m process, uses a supply voltage of 1.8 V, and provides an output mean voltage of about 6 V at 10 k/spl Omega/ resistive load with a 60-MHz external clock frequency.

Transport Physics and Device Modeling of Zinc Oxide Thin-Film Transistors Part I: Long-Channel Devices

A physical-based and analytical drain current model of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) is proposed. The model considers the combined contribution of both trapped and free charges that move through the a-IGZO film by multiple-trapping-and-release and percolation in conduction band. The model is compared with both measurements of TFTs fabricated on a flexible substrate and numerical simulations. It is accurate in the whole range of a-IGZO TFTs operation. The model requires only physical and geometrical device parameters. The resulting mathematical expressions are suitable for computer-aided design implementation and yield the material physical parameters that are essential for process characterization.

A fully integrated inductor-based 1.8-6-V step-up converter

A physically based mathematical model for the dc current of single-carrier organic light emitting diodes is presented. The model accounts for the most important physical quantities that influence the carrier mobility and thus the device current itself: temperature, charge carrier concentration, and electric field. It is rigorously developed basing on the variable range hopping transport theory and extends the pioneering work of Mark and Helfrich [J. Appl. Phys. 33, 205 (1962)] to large electric fields typical of light emitting diodes. It was validated on experimental data collected from devices of different materials in a wide range of operating conditions. Thanks to the effective electric field approach, the mathematical expression is simple, accurate and suitable for CAD applications.

Accurate Analytical Physical Modeling of Amorphous InGaZnO Thin-Film Transistors Accounting for Trapped and Free Charges

Abstract In this paper an analytical model for amorphous-silicon thin-film transistors is presented. The model accounts for a realistic distribution of states in the energy gap (both tail and deep states), and accurately describes the below-threshold, linear, and saturation regimes via a unique formulation.

Space-charge-limited current in organic light emitting diodes

In this paper, a mathematical model for the dc/dynamic current of organic thin-film transistors is proposed. The model is based on the variable-range hopping transport theory, i.e., thermally activated tunneling of carriers between localized states, and the mathematical expression of the current is formulated by means of the channel accumulation charge. It accurately accounts for below-threshold, linear, and saturation operating conditions via a single formulation, and does not require the explicit definition of the threshold and saturation voltages. Basing on the charge control approach, the dc model is straightforwardly generalized to dynamic conditions; the resulting mathematical expressions are simple and suitable for CAD applications.

A new analytical model for amorphous-silicon thin-film transistors including tail and deep states

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal–semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

A Charge-Based OTFT Model for Circuit Simulation

In this paper, a new charge pump architecture is presented: it is based on PMOS pass transistors with dynamic biasing of gates and bodies. By controlling the gate and body voltages of each pass transistor, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the other with negligible voltage drop. Furthermore, the overdrive voltage of the pass transistors grows progressively from the first to the last boost stage. This new architecture was developed and validated through simulations and experimental measurements on AMS 0.8/spl mu/m standard CMOS technology.