Zs. M. Kovács-Vajna

A fully integrated inductor-based 1.8-6-V step-up converter

To the authors knowledge, this is the first time that a paper demonstrates the feasibility of a fully integrated step-up converter based on inductive elements. The prototype is fabricated in the ST M8 0.18-/spl mu/m process, uses a supply voltage of 1.8 V, and provides an output mean voltage of about 6 V at 10 k/spl Omega/ resistive load with a 60-MHz external clock frequency.

A new integrated charge pump architecture using dynamic biasing of pass transistors

In this paper, a new charge pump architecture is presented: it is based on PMOS pass transistors with dynamic biasing of gates and bodies. By controlling the gate and body voltages of each pass transistor, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the other with negligible voltage drop. Furthermore, the overdrive voltage of the pass transistors grows progressively from the first to the last boost stage. This new architecture was developed and validated through simulations and experimental measurements on AMS 0.8/spl mu/m standard CMOS technology.

Analytical model for organic thin-film transistors operating in the subthreshold region

In this letter, a mathematical model for the subthreshold current of organic thin-film transistors (OTFTs) is proposed. The model is based on the variable range hopping transport theory using the channel depletion approach as in the standard junction field-effect transistor theory. Furthermore, the model is generalized to account for the complete depletion of the organic film. It describes the OTFTs behavior in the whole subthreshold region and it is suitable for computer aided design applications.

A charge control analytical model for organic thin film transistors

In this paper, a mathematical model for the dc current of organic thin film transistors is proposed. The model is based on the variable range hopping transport theory, while the mathematical expression of the current is formulated by means of the channel accumulation charge. It accurately accounts for below-threshold, linear, and saturation operating conditions via a single formulation and it does not require the explicit definition of the threshold and saturation voltages. Furthermore, thanks to the charge control approach, it is straightforwardly generalizable to dynamic behavior.

Robust design of bandgap voltage references with low EMI susceptibility

This paper addresses an approach to design bandgap voltage references which provides a good trade-off between overall performances and strong immunity to electromagnetic interferences. We investigated two classical topologies of bandgap references. The first circuit exhibits a 1200mV shift for interfering signals in the frequency range of 1MHz-4GHz, while the shift in the modified version of the same architecture is only 6mV. The second circuit exhibits a 300mV shift in the same frequency range while the shift in its modified version is only 20 mV.

A new lumped model for on-chip inductors including substrate currents

A new lumped model for on-chip planar (square, hexagonal, octagonal) inductors is presented. The model is simple, it is based on linear passive components with frequency independent parameters and accurately accounts for the substrate leakage currents in a wide frequency range. Furthermore, the model is straightforwardly implementable in circuit simulators such as, for example, SPICE.

High EMI immunity CMOS opamp: design and measurements

In this paper, a new approach to design a CMOS operational amplifier is presented which provides a good trade-off between high gain and strong immunity to electromagnetic interferences. The proposed amplifier is based on two main blocks: the first is a fully differential folded cascode amplifier with modified differential input pair and the second is a source cross coupled AB class buffer. Thanks to the folded cascade stage and to the symmetrical output buffer, the amplifier exhibits both intrinsic robustness to interferences and good amplifier performances. The circuit was fabricated in a 0.8/spl mu/m n-well CMOS technology (AMS CYE process). Experimental results, in terms of EMI immunity, are presented and successfully compared to commercial amplifiers. Measurements carried out on the chip and the amplifier overall performances are provided along with the corresponding simulation results.