Victor R. Gonzalez-Diaz

Efficient Dithering in MASH Sigma-Delta Modulators for Fractional Frequency Synthesizers

The digital multistage-noise-shaping (MASH) ΣΔ modulators used in fractional frequency synthesizers are prone to spur tone generation in their output spectrum. In this paper, the state of the art on spur-tone-magnitude reduction is used to demonstrate that an M -bit MASH architecture dithered by a simple M-bit linear feedback shift register (LFSR) can be as effective as more sophisticated topologies if the dither signal is properly added. A comparison between the existent digital ΣΔ modulators used in fractional synthesizers is presented to demonstrate that the MASH architecture has the best tradeoff between complexity and quantization noise shaping, but they present spur tones. The objective of this paper was to significantly decrease the area of the circuit used to reduce the spur tone magnitude for these MASH topologies. The analysis is validated with a theoretical study of the paths where the dither signal can be added. Experimental results of a digital M -bit MASH 1-1-1 ΣΔ modulator with the proposed way to add the LFSR dither are presented to make a hardware comparison.

A Pseudorandom Number Generator Based on Time-Variant Recursion of Accumulators

This brief presents a pseudorandom number generator that requires very low resources from the hardware design point of view. It is based on a chain of digital accumulators whose coefficients are varied by an auxiliary low-complexity linear feedback shift register. We present a predictability and periodicity analysis of the sequences generated by the proposed architecture to show that the system is a good candidate to be used for applications requiring high-quality pseudorandom sequences in portable devices. The statistical behavior of the proposed solution is also validated by tests from the National Institute of Standards and Technology. The generated pseudorandom sequences pass all tests at both the level-one and level-two approaches.

Accurate models for Frequency Synthesizers

An accurate Noise description in behavioral models for Fractional-N Frequency Synthesizers is presented. It is demonstrated that a noise-addition-like synthesizerpsilas model yields a better Phase-Noise prediction than a time-domain jitter model. This allows a more direct analysis of the noise contribution of every circuit in the Frequency Synthesizers and avoids simulation inaccuracies when very low Phase-Noise designs are held.

Pseudorandom sequence generation for mismatch analog compensation of ADCs

This paper presents a low complexity 1-bit pseudorandom number generator used in a digital background calibration for ADCs. The pseudorandom sequence generator is based on a chain of accumulators, with time-varied coefficients, that obtain a 1-bit sequence with good statistical properties. Behavioral simulations show that the convergence on the compensation algorithm in ADCs is improved.

Optimal dithered digital sigma-delta modulators for fractional-N frequency synthesizers

By using a structured dither addition it is demonstrated how a very simple 8-bit linear feedback shift register (LFSR) can be used to randomize a digital MASH 1-1-1 SigmaDelta modulator used for fractional-N frequency synthesizers. With this optimization, spur tones for high frequency offset from the carrier are avoided without significant area and power budget increase.

On the Electronic Realizations of Fractional-Order Phase-Lead-Lag Compensators with OpAmps and FPAAs

It is well known that the fractional-order phase-lead-lag compensators can achieve control objectives that are not always possible by using their integer-order counterparts. However, up to now one can find only a few of publications discussing the strategies for parameters’ tuning of these compensators, with only simulation results reported. This is due in part to the implicit difficulties on the implementation of circuit elements with frequency responses of the form \(s^{\pm \lambda }\) that are named “fractances”. In this regard, there exist approximations with rational functions, but the drawback is the difficulty to approximate the required values with the ones of the commercially-available resistances and capacitors. Consequently, fractional compensators have not been appreciated by the industry as it is in the academia. Therefore, motivated by the lack of reported implementations, this chapter is structured as a tutorial that deals with the key factors to perform, with the frequency-domain approach, the design, simulation and implementation of integer-order and fractional-order phase-lead-lag compensators. The circuit implementations are performed with Operational Amplifiers (OpAmps) and with Field Programmable Analog Arrays (FPAA). Emphasis is focused in the obtaining of commercially-available values of resistances and capacitors. Therefore, the design procedure starts with the use of equations that provide the exact and unique solution for each parameter of the compensator, avoiding conventional trial-and-error procedures. Then, five OpAmp-based configurations for integer-order and fractional-order realizations are described in terms of basic analog building blocks, such as integrators or differential amplifiers, among others. The corresponding design equations are also provided. Then, six examples are presented for both, OpAmp-based and FPAA-based implementations with the simulation and experimental results discussed regarding other results reported in the literature.

Improving linearity in MOS varactor based VCOs by means of the output quiescent bias point

This paper presents a CMOS based LC tank VCO topology improving the tuning range linearity. The VCO tuning range is linearized with PMOS varactors which remain in the inversion region for an extended range of the control voltage. This is achieved with the design of the quiescent operating point in the VCOs output nodes with a value close to the voltage rails, letting the varactors to behave quasi linearly in the achievable VCO tuning range. The experimental results of a VCO in a CMOS 0.35m process show a linear tuning range improvement of 75% of the control voltage in the (1.431.55)GHz range, with a minimum VCO gain variation compared to similar architectures. The results show a phase noise improvement from 94dBc/Hz to 124dBc/Hz @600kHz offset from the carrier with an overall reduced amplitude noise for the VCO. HighlightsThe VCO shows an improvement of linearity for the tuning range.The improvement is a consequence of the output quiescent point design.The comparison includes the VCO gain linearity, not considered in many works.Experimental results in a CMOS 0.35um attest the improvement in linearity.

ΣΔ Modulator with op-amp gain compensation for nanometer CMOS technologies

A gain compensated op-amp for discrete-time ΣΔ modulators is described. The method greatly reduces the integrators phase error caused by low DC gain on amplifiers. The scheme uses an additional unity gain buffer to correct the error caused by gains as low as 20 dB, thus enabling high-performance ΣΔ modulators in nanometer-scale CMOS technologies. Design strategies for op-amps and buffer designed with a 65 nm technology to be used with the method are considered. The effectiveness of the approach is verified with a second-order ΣΔ modulator simulated at behavioral level with MATLAB and Verilog-A descriptions. The low sensitivity to buffer gains variations is also verified.

New approximation for cosine wave mapping function to transistor level circuit

The present paper deals with the design of an analog circuit that allows generating the mapping of the cosine function. This design is based on a novel approximation form using electrical parameters of a 90nm Complementary Metal-Oxide-Semiconductor (CMOS) process. The proposed approach has been compared with other reported schemes. Owing to simplicity, the proposed analog circuit is suitable for high frequency applications and where the power resources are limited. As an example, the application of this circuit in the solution of a nonlinear ordinary differential equation is presented. This equation represents the model of the vertical dynamics of a PVTOL (Planar Vertical Take-off and Landing) system. The main advantage with the analog solution for trigonometric functions is a continuous time response at high frequency and with no quantization error.

Design constraints for low distortion OTA's in on-chip analog front-ends

This paper discusses design constraints for low distortion Operational Transconductance Amplifiers (OTAs) on integrated analog front ends. It also compares traditional OTA topologies and proposes a new OTA showing significant reduction on distortion for wideband applications, the comparison is presented on a 0.35μm CMOS process. The proposed OTA is designed for on-chip analog front ends for radiation gamma detectors on a 130nm CMOS process.