Lukas Dörrer

A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-/spl mu/m CMOS

A third-order continuous-time multibit (4 bit) /spl Delta//spl Sigma/ ADC for wireless applications is implemented in a 0.13-/spl mu/m CMOS process. It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of using a 4-bit flash quantizer. Moreover, the usage of a tracking ADC opens the door to a new forward-looking dynamic element matching (DEM) technique, which helps to reduce the loop delay time and consequently improves the loop stability. The SNR is 74 dB over a bandwidth of 2 MHz. The ADC consumes 3 mW from a 1.5-V supply when clocked at 104 MHz. The active area is 0.3 mm/sup 2/.

A 2.2mW, Continuous-Time Sigma-Delta ADC for Voice Coding with 95dB Dynamic Range in a 65nm CMOS Process

A second order continuous time multibit (4bit) DeltaSigma-ADC for voice coding is implemented in a 65nm CMOS process. The dynamic range (DR) is 95dB over the voice bandwidth of 20-20 000Hz. Furthermore, by using a feed back architecture the need of an anti aliasing filter is eliminated. The input operational amplifier is chopped to eliminate flicker noise and offset. These improvements give way to a substantial simplification of the analog front end by allowing the absorption of the pre-amplifier and the antialiasing filter into the DeltaSigma-ADC. Thanks to the feedback structure the slew rate at the quantizer is limited and a power-efficient tracking ADC can be used. The total harmonic distortion (THD) is below -77dB at maximum input signal of 1.4Vpp. The ADC consumes 2.2mW from a 1.2V supply when clocked at 12MHz. The active area is 0.149 mm2

A 3mW 74dB SNR 2MHz CT /spl Delta//spl Sigma/ ADC with a tracking-ADC-quantizer in 0.13 /spl mu/m CMOS

A third-order CT multibit /spl Delta//spl Sigma/ ADC for wireless applications is implemented in 0.13 /spl mu/m CMOS. Instead of using a 4b flash quantizer, a tracking ADC composed of 3 comparators with interpolation is used to reduce the power consumption. Over a bandwidth of 2MHz the SNR is 74dB. The ADC consumes 3mW from a 1.5V supply when clocked at 104MHz.

A mixer-filter combination of a direct conversion receiver for DVB-H applications in 65nm CMOS

A mixer and operational amplifier filter combination in 65 nm CMOS technology for DVB-H is presented. Special focus is laid on the design of the operational amplifier, which is a nested-Miller compensated, 3-stage feed-forward operational amplifier. Characteristic of the operational amplifier is the supply voltage of 2.5 V to enlarge the output signal swing of the operational amplifier. Cascodes are used avoiding the electrical destruction. The operational amplifier has a gain of 89 dB, a gain-bandwidth of 1.1 GHz, and phase margin of 53.3 deg at a load of 1 pF on each of the two differential outputs. The current consumption is 5.85 mA. This operational amplifier is used in a first-order low-pass filter after a passive mixer. This mixer-filter combination is characterized as well. A conversion gain of 24 dB and a bandwidth of 4 MHz are realized. Furthermore a noise figure of 16.1 dB and an IIP3 of +10dBm are achieved.