Thomas Hartig

A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOS

We present a 6-bit 1.2-GS/s flash-ADC with wide analog bandwidth and low power, realized in a standard digital 0.13 /spl mu/m CMOS copper technology. Employing capacitive interpolation gives various advantages when designing for low power: no need for a reference resistor ladder, implicit sample-and-hold operation, no edge effects in the interpolation network (as compared to resistive interpolation), and a very low input capacitance of only 400 fF, which leads to an easily drivable analog converter interface. Operating at 1.2 GS/s the ADC achieves an effective resolution bandwidth (ERBW) of 700 MHz, while consuming 160 mW of power. At 600 MS/s we achieve an ERBW of 600 MHz with only 90 mW power consumption, both from a 1.5 V supply. This corresponds to outstanding figure-of-merit numbers (FoM) of 2.2 and 1.5 pJ/convstep, respectively. The module area is 0.12 mm/sup 2/.

A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-/spl mu/m CMOS

A third-order continuous-time multibit (4 bit) /spl Delta//spl Sigma/ ADC for wireless applications is implemented in a 0.13-/spl mu/m CMOS process. It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of using a 4-bit flash quantizer. Moreover, the usage of a tracking ADC opens the door to a new forward-looking dynamic element matching (DEM) technique, which helps to reduce the loop delay time and consequently improves the loop stability. The SNR is 74 dB over a bandwidth of 2 MHz. The ADC consumes 3 mW from a 1.5-V supply when clocked at 104 MHz. The active area is 0.3 mm/sup 2/.

A digitally controlled DC-DC converter for SoC in 28nm CMOS

Battery operation in mobile applications needs power efficient DC-DC converters which are able to handle battery voltages up to 5.5V. Normally, these DC-DC converters are built in special technologies. For decreased footprint and chip count of the overall system, a system-on-chip solution on modern CMOS technology with core supply voltages around 1V is preferred. The presented DC-DC buck converter generates 0.9 to 1.8V at output currents up to 500mA from a battery voltage of 2.4 to 5.5V with high efficiency in a high-k 28nm metal-gate CMOS technology.

A 6bit, 1.2GSps low-power flash-ADC in 0.13 /spl mu/m digital CMOS

A 6 bit flash-ADC with 1.2 GSps, wide analog bandwidth and low power, realized in a standard digital 0.13 /spl mu/m CMOS copper technology is presented. Employing capacitive interpolation gives various advantages when designing for low power: no need for a reference resistor ladder, implicit sample-and-hold operation, no edge effects in the interpolation network (as compared to resistive interpolation), and a very low input capacitance of only 400 fF, which leads to an easily drivable analog converter interface. Operating at 1.2 GSps the ADC achieves an effective resolution bandwidth (ERBW) of 700 MHz, while consuming 160 mW of power. At 600 MSps we achieve an ERBW of 600 MHz with only 90 mW power consumption, both from a 1.5 V supply. This corresponds to outstanding figure-of-merit numbers (FoM) of 2.2 and 1.5 pJ/convstep, respectively. The module area is 0.12 mm/sup 2/.

A 2.2mW, Continuous-Time Sigma-Delta ADC for Voice Coding with 95dB Dynamic Range in a 65nm CMOS Process

A second order continuous time multibit (4bit) DeltaSigma-ADC for voice coding is implemented in a 65nm CMOS process. The dynamic range (DR) is 95dB over the voice bandwidth of 20-20 000Hz. Furthermore, by using a feed back architecture the need of an anti aliasing filter is eliminated. The input operational amplifier is chopped to eliminate flicker noise and offset. These improvements give way to a substantial simplification of the analog front end by allowing the absorption of the pre-amplifier and the antialiasing filter into the DeltaSigma-ADC. Thanks to the feedback structure the slew rate at the quantizer is limited and a power-efficient tracking ADC can be used. The total harmonic distortion (THD) is below -77dB at maximum input signal of 1.4Vpp. The ADC consumes 2.2mW from a 1.2V supply when clocked at 12MHz. The active area is 0.149 mm2

A high signal swing Class AB earpiece amplifier in 65nm CMOS Technology

This paper describes a new circuit solution to implement a high signal swing amplifier for driving a low resistive and high capacitive load. The amplifier is dedicated to operate at a supply voltage of 2.5V driving an earpiece device of a mobile phone by the usage of a standard digital single gate oxide transistor in a 65nm technology. The high linearity is achieved by using a three stage amplifier. To handle the high voltage of 2.5 V with the 1.2 V transistor an innovative transistor cascoding is implemented. A class AB output stage is chosen to ensure a low power consumption. A prototype is realized in a low power 65 nm CMOS technology. The measured THD is lower than 0.04% at the desired audio band of 20kHz

A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13/spl mu/m CMOS

A 14b multi-bit-per-stage pipelined ADC is implemented in a 0.13mum digital CMOS process. The gain and matching errors of the analog circuitry are compensated by a digital calibration scheme that allows the usage of a low-gain op-amp. A low power consumption has been reached by introducing a charge compensation scheme

A 6bit, 1.2GSps low-power flash-ADC in 0.13/spl mu/m digital CMOS

A 6 bit flash-ADC with 1.2 GSps, wide analog bandwidth and low power, realized in a standard digital 0.13 /spl mu/m CMOS copper technology is presented. Employing capacitive interpolation gives various advantages when designing for low power: no need for a reference resistor ladder, implicit sample-and-hold operation, no edge effects in the interpolation network (as compared to resistive interpolation), and a very low input capacitance of only 400 fF, which leads to an easily drivable analog converter interface. Operating at 1.2 GSps, the ADC achieves an effective resolution bandwidth (ERBW) of 700 MHz, while consuming 160 mW of power. At 600 MSps we achieve an ERBW of 600 MHz with only 90 mW power consumption, both from a 1.5 V supply. This corresponds to outstanding figure-of-merit numbers (FoM) of 2.2 and 1.5 pJ/convstep, respectively. The module area is 0.12 mm/sup 2/.