A.M. Waite

High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture

Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si/sub 0.7/Ge/sub 0.3/ on an Si/sub 0.85/Ge/sub 0.15/ virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process.

Effective mobilities in pseudomorphic Si/SiGe/Si p-channel metal-oxide-semiconductor field-effect transistors with thin silicon capping layers

The room-temperature effective mobilities of pseudomorphic Si/Si0.64Ge0.36/Si p-metal-oxidesemiconductor field effect transistors are reported. The peak mobility in the buried SiGe channel increases with silicon cap thickness. It is argued that SiO2/Si interface roughness is a major source of scattering in these devices, which is attenuated for thicker silicon caps. It is also suggested that segregated Ge in the silicon cap interferes with the oxidation process, leading to increased SiO2/Si interface roughness in the case of thin silicon caps.

Si/Si(0.64)Ge(0.36)/Si pMOSFETs with Enhanced Voltage Gain and Low 1/f Noise

Si/Si0.64Fe0.36/Si p MOSFETs with written gate lengths in the range 0.5mu micron to 10mu micron have been fabricated in a reduced thermal budget variant of a standard CMOS process. The devices exhibit enhanced maximum voltage-gains and reduced 1/f noise as compared to silicon controls.

Low-frequency noise mechanisms in Si and pseudomorphic SiGe p-channel field-effect transistors

Measurements of low frequency noise in Si and Si0.64Ge0.36 p-channel metal oxide semiconductor field effect transistors are compared with a model of carrier number fluctuations due to tunneling into an energy independent density of oxide trap states (Nox) and associated mobility fluctuations. The failure of the model to explain the data leads us to suggest that reduced noise in the SiGe device as compared to Si is primarily associated with an energy dependence of Nox and a displacement of the Fermi level at the SiO2 interface in the heterostructure relative to the Si control.

Enhanced Velocity Overshoot and Transconductance in Si/Si(0.64)Ge(0.36)/Si pMOSFETs - Predictions for Deep Submicron Devices

Electrical measurements have been carried out on Si/Si 0.64 Ge 0.36/Si pMOS devices and it is demonstrated that enhanced low field carrier mobilities lead to concomitant and substantial enhancements in velocity overshoot and transconductance at deep submicron channel lengths. This provides considerable motivation for incorporating SiGe into Si MOS technology.

SiGe CMOS fabrication using SiGe MBE and anodic/LTO gate oxide

An investigation of an SiGe CMOS process fulfilling low-thermal-budget requirements was carried out. Three different undoped layers were grown successively by MBE: a 20 nm buffer layer, a 15 nm SiGe layer and a 15 nm cap layer. The Ge concentration of the SiGe layer was either uniform 20% or linearly graded 0-40% from the substrate to the surface. A 50 nm thick undoped Si layer was grown for the reference devices. Anodic oxide and LTO were used as gate dielectrics. The annealing was performed at relatively modest temperatures. The SiGe p-MOSFETs were compared to the Si reference devices. We report an enhancement of the hole mobility up to 70% for the SiGe p-MOSFETs.

Transconductance, carrier mobility and 1/f noise in Si/Si0.64Ge0.36/Si pMOSFETs

We briefly review recent work on enhancements in transconductance, maximum voltage gain, carrier mobility and velocity overshoot in Si/Si0.64Ge0.36/Si p-channel metal-oxide semiconductor devices and then discuss the superior 1/f noise properties in more detail. The results indicate the growth and processing chanllenges which must be met in order to improve device performance.

Halo implant in pseudomorphic SiGe channel p-MOSFET devices to reduce short channel effect

Halo ion implantation was adopted to reduce the short channel effect (SCE) of a buried channel p-MOSFET device on pseudomorphic Si0.70Ge0.30 layers. The strained pseudomorphic Si0.70Ge0.30 layer of 10 nm thickness, with a Si cap layer on top, was grown using molecular beam epitaxy. The results show an overall reduction in threshold voltage (Vth) roll-off in both Si and pseudomorphic SiGe devices. Halo implantation of As+, 120 keV and dose 2 × 1013 cm−2, was successfully used to reduce roll-off for the 2 nm Si cap SiGe device by 0.3 V. However, it was found that halo implantation causes the reverse short channel effect (RSCE) on the devices, which can result in Vth roll-up with reducing channel length. The effect of the RSCE becomes greater with increasing Si cap thicknesses of the SiGe devices. Also, non-halo implanted devices were found to demonstrate the RSCE. This is due to excess interstitials from the source/drain implant and their subsequent diffusion, which causes virtual halo dopant to form in non-halo implanted devices.

Indication of Non-equilibrium Transport in SiGe p-MOSFETs

We have investigated the high field transport in CMOS compatible Si0.64Ge0.36 p-MOSFETs with various gate lengths for two different Si cap thicknesses. Using a fully calibrated Drift Diffusion and Energy Transport models, we have obtained good agreement with measurements across the entire range of voltages and gate lengths. Our results clearly indicate the presence of nonequilibrium transport in SiGe channels, which results from larger energy relaxation times in pseudomorphic SiGe layers in comparison with Si.

SiGe pMOSFETs Fabricated on Limited Area SiGe Virtual Substrates

Silicon germanium pMOSFETs with channel lengths down to 0.4m have been fabricated on limited area silicon germanium virtual substrates. The devices have a 5nm thick Si 0.3 Ge 0.7 active layer grown by MBE on top of relaxed Si 0.7 Ge 0.3 virtual substrate. Virtual substrates were grown on top of 10μm square silicon pillars defined by etching trenches around their perimeter into the original silicon substrate. This limits the area of the growth zone, which in turn promotes the relaxation of the virtual substrate. Electrical measurements on 2μm long channel devices show that the maximum mobility in the strained SiGe devices is 211cm 2 V -1 cm -1 , compared to 104cm 2 V -1 cm -1 for silicon reference devices. This increase in hole mobility increases the current drive of 0.4m devices measured at V gt =-2V, V ds =-2.5V from 154μA/m to 192μA/μm.